Mobile LPDDR4 SDRAM,MT53B256M32D1, MT53B512M32D2, MT53B1024M32D4,Features • Ultra-low-voltage core and I/O power supplies – VDD1 = 1.70–1.95V; 1.8V nominal – VDD2/VDDQ = 1.06–1.17V; 1.10V nominal • Frequency range – 1600–10 MHz (data rate range: 3200–20 Mb/s/ pin) • 16n prefetch DDR architecture • 2-channel partitioned architecture for low RD/WR energy and low average latency • 8 internal banks per channel for concurrent operation • Single-data-rate CMD/ADR entry • Bidirectional/differential data strobe per byte lane • Programmable READ and WRITE latencies (RL/WL) • Programmable and on-the-fly burst lengths (BL = 16, 32) • Directed per-bank refresh for concurrent bank operation and ease of command scheduling • Up to 12.8 GB/s per die (2 channels x 6.4 GB/s) • On-chip temperature sensor to control self refresh rate • Partial-array self refresh (PASR) • Selectable output drive strength (DS) • Clock-stop capability • RoHS-compliant, “green” packaging • Programmable VSSQ (ODT) termination