LCD1602显示英文字符实验FPGA（EP4CE6）Verilog例程quartus11.0工程源码，可以做为你的学习设计参考。 module lcd(clk, rs, rw, en,dat); input clk; output [7:0] dat; output rs,rw,en; //tri en; reg e; reg [7:0] dat; reg rs; reg [15:0] counter; reg [4:0] current,next; reg clkr; reg [1:0] cnt; parameter set0=4'h0; parameter set1=4'h1; parameter set2=4'h2; parameter set3=4'h3; parameter dat0=4'h4; parameter dat1=4'h5; parameter dat2=4'h6; parameter dat3=4'h7; parameter dat4=4'h8; parameter dat5=4'h9; parameter dat6=4'hA; parameter dat7=4'hB; parameter dat8=4'hC; parameter dat9=4'hD; parameter dat10=4'hE; parameter dat11=5'h10; parameter nul=4'hF; always @(posedge clk) begin counter=counter+1; if(counter==16'h000f) clkr=~clkr; end always @(posedge clkr) begin current=next; case(current) set0: begin rs<=0; dat<=8'h30; next<=set1; end set1: begin rs<=0; dat<=8'h0c; next<=set2; end set2: begin rs<=0; dat<=8'h6; next<=set3; end set3: begin rs<=0; dat<=8'h1; next<=dat0; end dat0: begin rs<=1; dat<="H"; next<=dat1; end dat1: begin rs<=1; dat<="E"; next<=dat2; end dat2: begin rs<=1; dat<="L"; next<=dat3; end dat3: begin rs<=1; dat<="L"; next<=dat4; end dat4: begin rs<=1; dat<="O"; next<=dat5; end dat5: begin rs<=1; dat<=" "; next<=dat6; end dat6: begin rs<=1; dat<="W"; next<=dat7; end dat7: begin rs<=1; dat<="O"; next<=dat8; end dat8: begin rs<=1; dat<="R"; next<=dat9; end dat9: begin rs<=1; dat<="L"; next<=dat10; end dat10: begin rs<=1; dat<="D"; next<=dat11; end dat11: begin rs<=1; dat<="!"; next<=nul; end nul: begin rs<=0; dat<=8'h00; //行一遍 然后 把液晶的E 脚 拉高 if(cnt!=2'h2) begin e<=0;next<=set0;cnt<=cnt+1; end else begin next<=nul; e<=1;

LCD1602显示屏显示字符实验FPGA设计Verilog逻辑源码Quartus11.0工程文件，FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module my1602(clk,RS,RW,E,Data,back_light); input clk; //50MHZ时钟的输入 output RS,RW,E; //1602的控制信号使能，数据/命令，读/写 output [7:0]Data; //数据端 output back_light; //背光 reg RS; reg [7:0]Data; parameter address=8'h80; //第一行 parameter address2=8'hc0; //第二行 assign RW=1'b0; //只用显示时，一直是写的状态 assign back_light=1'b1; //背光灯打开 reg clk_e; reg [15:0]count; always @(posedge clk) begin count=count+1'b1; if(count==16'hf000) begin clk_e=~clk_e; //作为使能端 count=16'd0; end end reg [1:0]jishu; reg [4:0]zhuangtai; //状态机状态 reg temp; always @(posedge clk_e) begin case(zhuangtai) 5'b00000:begin temp<=1'b0; RS<=1'b0; Data<=8'h38;//显示模式设置 zhuangtai<=zhuangtai+1'b1; end 5'b00001:begin RS<=1'b0; Data<=8'h0c;//显示开及光标设置 zhuangtai<=zhuangtai+1'b1; end 5'b00010:begin RS<=1'b0; Data<=8'h06;//显示光标移动设置 zhuangtai<=zhuangtai+1'b1; end 5'b00011:begin RS<=1'b0; Data<=8'h01;//显示

LCD1602屏 (EP4CE30) FPGA读写实验Verilog逻辑源码Quartus工程文件+文档资料。FPGA为CYCLONE4系列中的EP4CE30F23C8. 完整的工程文件，可以做为你的学习设计参考。 module LCD1602_Cnt(input sys_clk, //50M input sys_rst_n, output reg lcd_rs, //0:write order; 1:write data output lcd_rw, //0:write data; 1:read data output reg lcd_en, // output reg [7:0] lcd_data); //--------------------lcd1602 order---------------------------- parameter Mode_Set = 8'h38, //������ʾģʽ��8λ2��5x8���� Cursor_Set = 8'h0c, //��ʾ������겻��ʾ�����겻������˸ Address_Set = 8'h06, //���ֲ����������Զ����� Clear_Set = 8'h01; //��������긴λ /****************************LCD1602 Display Data****************************/ wire [7:0] data0,data1; //counter data wire [7:0] addr; //write address //---------------------------------1s counter----------------------------------- reg [25:0] cnt1; reg [7:0] data_r0,data_r1; always@(posedge sys_clk or negedge sys_rst_n) begin if(!sys_rst_n) begin cnt1 <= 1'b0; data_r0 <= 1'b0; data_r1 <= 1'b0; end else if(cnt1==26'd50000000) begin if(data_r0==8'd9) begin data_r0 <= 1'b0; if(data_r1==8'd9) data_r1 <= 1'b0; else data_r1 <= data_r1 + 1'b1; end else data_r0 <= data_r0 + 1'b1; cnt1 <= 1'b0; end else cnt1 <= cnt1 + 1'b1; end assign data0 = 8'h30 + data_r0 ; assign data1 = 8'h30 + data_r1 ; //-------------------address------------------ assign addr = 8'h80; /****************************LCD1602 Driver****************************/ //-----------------------lcd1602 sys_clk_en--------------------- reg