在Cadence平台中，用Verilog-A产生正弦抖动的时钟。用于SerDes接收机抖动容限的仿真。

抖动入门指南，抖动测量分析 jitter analysis

jitter测量定义，测量方法，测量评估，应用文档，参考

时钟抖动问题很常见，也是笔试面试常考的内容，该文档提供了时钟抖动的定义以及测量方式，对于想要了解时钟抖动的学生以及专业人士可以参考。

作曲视觉音乐 一组用于生成视听效果的 Max/MSP/Jitter 工具

主要描述相噪及jitter的概念及其估算方法，并讲叙布置PCB时应如何降低相噪抖动

jitter和skew介绍与区别

主要介绍高速信号线中传输下jitter的产生原理及量测介绍

科技文献,clock jitter是串行系统重要参数

Clock generators play a key role in designs today. In the pursuit of high-speed, many systems have adopted synchronous design styles. With this methodology comes the need for a variety of frequencies and many copies of the same clock. In most systems, these clocks need to be in phase with one another. If they are not, precious cycle time is lost. Skew between clocks becomes very important in keeping all of the devices operating at their peak rates. Specialized clock buffers have led the way in providing clean, accurate clock signals.