基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的 TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 timescale 1ps/1ps module top ( input clk, input rst_n, output[1:0] led, output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16 ; //external memory user interface data width parameter ADDR_BITS = 24 ; //external memory user interface address width parameter BUSRT_BITS = 10 ; //external memory user interface burst width parameter BURST_SIZE = 128 ; //burst size wire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clock wire wr_burst_finish; // from external memory controller,burst write finish wire rd_burst_finish; // from external memory controller,burst read finish wire rd_burst_req; // to external memory controller,send out a burst read request wire wr_burst_req; // to external memory controller,send out a burst write request wire[BUSRT_BITS - 1:0] rd_burst_len; // to e