FPGA设计控制蜂鸣器播放音乐实验的Verilog逻辑源码Quartus工程文件+文档说明，根据简谱不同简谱名频率让蜂鸣器发出不一样的响声，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module music_top ( input clk, input rst_n, input key1, output reg buzzer ) ; parameter CLK_FRE = 50 ; parameter music_len = 32'd78 ; wire [19:0] cycle ; reg [31:0] play_cnt ; reg [31:0] music_cnt ; reg [19:0] hz_cnt ; wire [4:0] hz_sel ; wire [7:0] rom_hz_data ; wire [7:0] rom_time_data ; reg [31:0] music_time ; wire button_negedge ; parameter IDLE = 2'd0 ; parameter PLAY = 2'd1 ; parameter PLAY_WAIT = 2'd2 ; parameter PLAY_END = 2'd3 ; reg [1:0] state ; reg [1:0] next_state ; always @(posedge clk or negedge rst_n) begin if (~rst_n) state <= IDLE ; else state <= next_state ; end always @(*) begin case(state) IDLE : begin if (button_negedge) next_state <= PLAY ; else next_state <= IDLE ; end PLAY : begin if (play_cnt == music_time) next_state <= PLAY_WAIT ; else next_state <= PLAY ; end PLAY_WAIT : begin if (music_cnt == music_len - 1) next_state <= PLAY_END ; else next_state <= PLAY ; end PLAY_END : next_state <= IDLE ; default : next_state <= IDLE ; endcase end ax_debounce ax_debounce_a0 ( .clk (clk), .rst (~rst_n), .button_in (key1), .button_posedge (), .button_negedge (button_negedge), .button_out () ); //play counter always @(posedge clk or negedge rst_n) begin if (~rst_n) music_time <= 32'hffff_ffff ; else music_time <= rom_time_data*(CLK_FRE*1000000/8) ; end //counter in every step, maximum value is cycle always @(posedge clk or negedge rst_n) begin if (~rst_n) hz_cnt <= 20'd0 ; else if (state == PLAY || state == PLAY_WAIT) begin if (hz_cnt == cycle - 1) hz_cnt <= 20'd0 ; else hz_cnt <=