Cyclone4 FPGA读写高速AD-TLC549+DA-AD9708模块实验Verilog逻辑源码Quartus工程+文档资料
module DA_AD9708_BASE (
//input
input sys_clk , //system clock;
// input sys_rst_n , //system reset, low is active;
input [3:0] key ,
//output
output reg [7:0] DA_DATA ,
output reg DA_CLK ,
output reg [7:0] LED
);
//Reg define
reg [7:0] div_cnt ;
//Wire define
//************************************************************************************
//** Main Program
//**
//************************************************************************************
assign sys_rst_n = 1'b1 ;
// counter used for div osc clk to ad ctrl clk 50M/4 = 12.5Mhz
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
div_cnt <= 8'b0;
else
div_cnt <= div_cnt + 8'b1;
end
//gen DA_CLK
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
DA_CLK <= 1'b0 ;
else if ( div_cnt == 8'd0 )
DA_CLK <= ~DA_CLK ;
else ;
end
//display AD sample data to LED
always @(posedge DA_CLK or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
DA_DATA <= 8'b0;
else
DA_DATA <= { key, key };
end
//display AD sample data to LED
always @(posedge DA_CLK or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
LED <= 8'b0;
else
LED <= { key, key } ;
end
2021-09-02 14:08:53
7.17MB