Cyclone10 FPGA读写MP25P16 spiflash实验Verilog源码Quartus17.1工程文件+文档资料,, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。
module spi_flash_top(
input sys_clk,
input rst,
output nCS,
output DCLK,
output MOSI,
input MISO,
input[15:0] clk_div,
input[3:0] cmd,
input cmd_valid,
output cmd_ack,
input[23:0] addr,
input[7:0] data_in,
input[8:0] size,
output data_req,
output reg[7:0] data_out,
output reg data_valid
);
localparam S_IDLE = 0;
localparam S_SE = 1;
localparam S_BE = 2;
localparam S_READ = 3;
localparam S_WRITE = 4;
localparam S_ACK = 5;
localparam S_CK_STATE = 6; //present state monitor
localparam S_WREN = 7;
wire spi_flash_cmd_ack;
reg[3:0] sub_cmd;
reg sub_cmd_valid;
reg[8:0] sub_size;
reg[4:0] state,next_state;
reg[7:0] state_reg;
wire sub_data_valid;
wire[7:0] sub_data_in;
wire[7:0] sub_data_out;
assign sub_data_in = data_in;
assign cmd_ack = (state == S_ACK);
always@(posedge sys_clk or posedge rst)
begin
if(rst==1)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)
begin
case(state)
S_IDLE:
if(cmd_valid && cmd == `CMD_BE)
next_state <= S_WREN;
else if(cmd_valid && cmd == `CMD_SE)
next_state <= S_WREN;
else if(cmd_valid && cmd == `CMD_READ)
next_state <= S_READ;
else if(cmd_valid && cmd == `CMD_PP)
next_state <= S_WREN;
else
next_state <= S_IDLE;
S_WREN:
if(spi_flash_cmd_ack && cmd == `CMD_BE)
next_state <= S_BE;
else if(spi_flash_cmd_ack && cmd == `CMD_SE)
next_state <= S_SE;
else if(spi_flash_cmd_ack && cmd == `CMD_PP)
next_state <= S_WRITE;
else
next_state <= S_WREN;
S_BE:
if(spi_flash_cmd_ack)
next_state <= S_CK_STATE;//读取状态寄存器
else
next_state <= S_BE;
S_SE:
if(spi_flash_cmd_ack)
next_state <= S_CK_STATE;
2021-12-12 09:08:55
4.81MB
Cyclone10 FPGA读写eeprom(24lc04)实验Verilog源码Quartus17.1工程文件+文档资料, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。
module i2c_master_top
(
input rst,
input clk,
input[15:0] clk_div_cnt,
// I2C signals
// i2c clock line
input scl_pad_i, // SCL-line input
output scl_pad_o, // SCL-line output(always 1'b0)
output scl_padoen_o, // SCL-line output enable(active low)
// i2c data line
input sda_pad_i, // SDA-line input
output sda_pad_o, // SDA-line output (always 1'b0)
output sda_padoen_o, // SDA-line output enable (active low)
input i2c_addr_2byte,
input i2c_read_req,
output i2c_read_req_ack,
input i2c_write_req,
output i2c_write_req_ack,
input[7:0] i2c_slave_dev_addr, //device address
input[15:0]i2c_slave_reg_addr, //word address
input[7:0] i2c_write_data,
output reg[7:0]i2c_read_data,
output reg error
);
localparam S_IDLE = 0;
localparam S_WR_DEV_ADDR = 1;
localparam S_WR_REG_ADDR = 2;
localparam S_WR_DATA = 3;
localparam S_WR_ACK = 4;
localparam S_WR_ERR_NACK = 5;
localparam S_RD_DEV_ADDR0 = 6;
localparam S_RD_REG_ADDR = 7;
localparam S_RD_DEV_ADDR1 = 8;
localparam S_RD_DATA = 9;
localparam S_RD_STOP = 10;
localparam S_WR_STOP = 11;
localparam S_WAIT = 12;
localparam S_WR_REG_ADDR1 = 13;
localparam S_RD_REG_ADDR1 = 14;
localparam S_RD_ACK = 15;
reg start;
reg stop;
reg read;
reg write;
reg ack_in;
reg[7:0] txr;
wire[7:0] rxr;
wire i2c_busy; //It was high level after start signal and low level after stop signal
wire i2c_al; //arbitrament lose(The stop signal is detected but no signal is requested.The host setting SDA is high,Actual SDA is low)
wire done;
wire irxack; //slave receive the respond，0 (receive)，1(refuse)
reg[3:0] state,next_state;
assign i2c_read
2021-12-11 21:02:03
5.87MB