Assertion-based IP. The design of systems in the 21st century is necessarily one
of decomposition of product requirements into functional
subsystems. Often these subsystems are implemented with a
mix of commercial and in-house design IP. In order to fit
into a modern design flow, each design IP should be
accompanied by a verification IP (VIP) and a verification
plan IP (VPIP). If an electronic system level (ESL) design
flow is employed, the VIP and VPIP are employed twice in
the flow: during post-partitioning verification and
implementation verification. In post-partitioning
verification, the behavior of the abstract hardware and
software models is demonstrated to conform to their
functional specifications. During implementation
verification, the behavior of the RTL and embedded
production software is demonstrated to conform with the
behavior of their corresponding abstract models, as well as
with implementation requirements captured in design
specifications. Hence, the role of VIP and VPIP is becoming
increasingly important, requiring rigorous development
processes.
Verification IP is available across
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