This lecture presents a study of the microarchitecture of contemporary microprocessors. The fo-
cus is on implementation aspects, with discussions on their implications in terms of performance,
power, and cost of state-of-the-art designs. The lecture starts with an overview of the different types
of microprocessors and a review of the microarchitecture of cache memories. Then, it describes
the implementation of the fetch unit, where special emphasis is made on the required support for
branch prediction. The next section is devoted to instruction decode with special focus on the par-
ticular support to decoding x86 instructions. The next chapter presents the allocation stage and pays
special attention to the implementation of register renaming. Afterward, the issue stage is studied.
Here, the logic to implement out-of-order issue for both memory and non-memory instructions is
thoroughly described. The following chapter focuses on the instruction execution and describes the
different functional units that can be found in contemporary microprocessors, as well as the imple-
mentation of the bypass network, which has an important impact on the performance. Finally, the
lecture concludes with the commit stage, where it describes how the architectural state is updated
and recovered in case of exceptions or misspeculations.
This lecture is intended for an advanced course on computer architecture, suitable for gradu-
ate students or senior undergrads who want to specialize in the area of computer architecture. It
is also intended for practitioners in the industry in the area of microprocessor design. The book
assumes that the reader is familiar with the main concepts regarding pipelining, out-of-order execu-
tion, cache memories, and virtual memory.
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