2N分頻器5分頻器10分頻器分頻器器VHDL逻辑设计源码Quartus工程文件, Quartus软件版本9.0,可以做为你的学习设计参考。
ibrary ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity clk_8div is
port(
clk:in std_logic;
clk_div2:out std_logic;
clk_div4:out std_logic;
clk_div8:out std_logic);
end clk_8div;
architecture rtl of clk_8div is
signal counter :std_logic_vector(2 downto 0);
begin
process(clk)
begin
if(clk'event and clk='1') then
if(counter="111") then
counter'0');
else
counter<=counter+1;
end if;
end if;
end process;
clk_div2<=not counter(0);--ȡ��һλ
clk_div4<=not counter(1);
clk_div8<=not counter(2);
end rtl;