d卡实验Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。
module sd_card_test(
input clk,
input rst_n,
input key1,
output SD_nCS,
output SD_DCLK,
output SD_MOSI,
input SD_MISO,
output [5:0] seg_sel,
output [7:0] seg_data
);
parameter S_IDLE = 0;
parameter S_READ = 1;
parameter S_WRITE = 2;
parameter S_END = 3;
reg[3:0] state;
wire sd_init_done;
reg sd_sec_read;
wire[31:0] sd_sec_read_addr;
wire[7:0] sd_sec_read_data;
wire sd_sec_read_data_valid;
wire sd_sec_read_end;
reg sd_sec_write;
wire[31:0] sd_sec_write_addr;
reg [7:0] sd_sec_write_data;
wire sd_sec_write_data_req;
wire sd_sec_write_end;
reg[9:0] wr_cnt;
reg[9:0] rd_cnt;
wire button_negedge;
reg[7:0] read_data;
ax_debounce ax_debounce_m0
(
.clk (clk),
.rst (~rst_n),
.button_in (key1),
.button_posedge (),
.button_negedge (button_negedge),
.button_out ()
);
wire[6:0] seg_data_0;
seg_decoder seg_decoder_m0(
.bin_data (read_data[3:0]),
.seg_data (seg_data_0)
);
wire[6:0] seg_data_1;
seg_decoder seg_decoder_m1(
.bin_data (read_data[7:4]),
.seg_data (seg_data_1)
);
seg_scan seg_scan_m0(
.clk (clk),
.rst_n (rst_n),
.seg_sel (seg_sel),
.seg_data (seg_data),
.seg_data_0 ({1'b1,7'b1111_111}),
.seg_data_1 ({1'b1,7'b1111_111}),
.seg_data_2 ({1'b1,7'b1111_111}),
.seg_data_3 ({1'b1,7'b1111_111}),
.seg_data_4 ({1'b1,seg_data_1}),
.seg_data_5 ({sd_init_done,seg_data_0})
);
always@(posedge clk or negedge rst_n)
begin
if(rst_n == 1'b0)
wr_cnt <= 10'd0;
else if(state == S_WRITE)
begin
if(sd_sec_write_data_req == 1'b1)
wr_cnt <= wr_cnt + 10'
2021-04-13 15:03:07
7.58MB