一个运用FPGA产生波形的电路。
module lcnt(clk,rst_n,ld,d,cao);
input clk;
input ld;
input [7:0]d;
input rst_n;
output cao;
reg [7:0] count;
reg cao;
always@(posedge clk )
begin
if (!rst_n) begin
count<=8'b00000000;
end
else if (ld) begin
count<=d;
end
else begin
count<=count+1'b1;
end
end
always@(posedge clk)
begin
if (count==255) begin
cao<=1'b0;
end
end
endmodule
2021-09-09 22:30:39
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