FPGA(EP4CE6)控制步进电机实验Verilog逻辑源码Quartus工程文件+文档资料, module STEP_MOTO_V1_0 ( //input input sys_clk , input [3:0] key , output reg mot_out_a , output reg mot_out_b , output reg mot_out_c , output reg mot_out_d ); //reg define reg [8-1:0] counter ; reg [8-1:0] count ; reg [25:0] clk_cnt ; reg [ 2:0] step_cnt ; //wire wire step_en ; //wire define //parameter define assign sys_rst_n = 1'b1 ; // gen a time counter , 5500000 * 20ns always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) clk_cnt <= 26'b0; else if ( clk_cnt == 26'd500000 ) clk_cnt <= 26'b0; else clk_cnt <= clk_cnt + 26'b1; end // step enable is active 5500000 * 20ns assign step_en = ( clk_cnt == 26'b0 ) ? 1:0 ; always @(posedge step_en or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) step_cnt <= 3'b0; else step_cnt <= step_cnt + 3'b1; end always @(posedge step_en or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) begin mot_out_a <= 1'b0; mot_out_b <= 1'b0; mot_out_c <= 1'b0; mot_out_d <= 1'b0; end else if ( step_cnt == 0 ) begin mot_out_a <= 1'b0; // 6 mot_out_b <= 1'b0; mot_out_c <= 1'b0; mot_out_d <= 1'b1; end else if ( step_cnt == 1 ) begin mot_out_a <= 1'b0; mot_out_b <= 1'b0; mot_out_c <= 1'b1; mot_out_d <= 1'b1; end else if ( step_cnt == 2 ) begin mot_out_a <= 1'b0;