全加器是算术运算电路运算中的基本单元，也是构成多位加法器的基本单元，介于加法器在算术运算电路当中的重要作用，使得全加器的设计显得十分重要。通常情况下，我们采用两种结构构成全加器电路，一种是由两个半加器组成，另一种为镜像结构。本文主要介绍一个镜象结构电路的一位全加器的设计，包括电路图，基于0.18CMOS工艺的版图，以及前端网表的仿真，后端版图的验证结果。

数字电路CMOS&TTL74系列芯片ALTIUM库（AD原理图库），包括CMOS4000和TTL74 2个系列芯片全部型号原理图库文件，共896个 Library Component Count : 896 4020 14-Stage Ripple-Carry Binary Counter 4021 8-Stage Shift Register (Asynchronous Parallel Input or Synchronous Serial Input/Serial Output) 4022 Octal Counter with 8 Decoded Outputs 4023 Triple 3-Input NAND Gate 4024 7-Stage Ripple-Carry Binary Counter 4025 Triple 3-Input NOR Gate 4027 Dual J-K Master-Slave Flip-Flop 4028 BCD to Decimal Decoder 4029 Presettable Up/Down Counter Binary or BCD Decade 4030 Quad Exclusive-OR Gate 4031 64-Stage Static Shift Register 4035 4-Stage Parallel In/Parallel Out Shift Register 4040 12-Stage Ripple-Carry Binary Counter 4041 Quad True/Complement Buffer 4042 Quad Clocked D-Latch 4043 Quad 3-State R-S Latch 4044 Quad 3-State R-S Latch 4049 Inverting Hex Buffer / Converter 4050 Non-Inverting Hex Buffer/Conver 74F14 Hex Schmitt-Trigger Inverter 74F148 8-Line to 3-Line Priority Encoder 74F151 1 of 8 Data Selector/Multiplexer 74F151A 1 of 8 Data Selector/Multiplexer 74F153 Dual 4-Line to 1-Line Data Selector/Multiplexer 74F154 4-Line to 16-Line Decoder/Demultiplexer 74F157 Quad 2-Line to 1-Line Data Selector/Multiplexer 74F157A Quad 2-Line to 1-Line Data Selector/Multiplexer 74F158 Quad 2-Line to 1-Line Data Selector/Multiplexer 74F158A Quad 2-Line to 1-Line Data Selector/Multiplexer 74F160A Synchronous 4-Bit Decade Counter with Direct Clear 74F161A Synchronous 4-Bit Binary Counter with Direct Clear 74F162A Fully Synchronous 4-Bit Decade Counter 74F163A Fully Synchronous 4-Bit Bina