完美时序-时钟产生和分发设计指南(中文版).pdf 完美时序-时钟产生和分发设计指南(中文版).pdf 完美时序-时钟产生和分发设计指南(中文版).pdf
2021-12-13 01:05:26 4.13MB 时序 时钟 设计指南 中文版
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Clock generators play a key role in designs today. In the pursuit of high-speed, many systems have adopted synchronous design styles. With this methodology comes the need for a variety of frequencies and many copies of the same clock. In most systems, these clocks need to be in phase with one another. If they are not, precious cycle time is lost. Skew between clocks becomes very important in keeping all of the devices operating at their peak rates. Specialized clock buffers have led the way in providing clean, accurate clock signals.
2021-12-13 01:04:29 3.12MB perfect timi Jitter PLL
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