VHDL Quartus 四分频器源代码 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ---------------------------------------------- ENTITY clk_div IS PORT( clk: IN STD_LOGIC;--时钟输入 clk_div2: OUT STD_LOGIC; clk_div4: OUT STD_LOGIC; clk_div8: OUT STD_LOGIC; clk_div16: OUT STD_LOGIC ); END ENTITY clk_div; --------------------------------------------------- ARCHITECTURE rtl OF clk_div IS