MINIUSB接口供电EPM240 CPLD三色LEDE灯爱心灯板Protel99se设计硬件原理图PCB+VERILOG 逻辑工程源码文件,硬件2层板设计,大小为66x57mm,Protel 99se 设计的DDB后缀项目工程文件,包括完整无措的原理图及PCB印制板图,已经制板测试使用,可用Protel或 Altium Designer(AD)软件打开或修改,可作为你产品设计的参考。
CPLD芯片为MAX2系列中的EPM240T100C5,2版3色流水灯及灯闪DEMO QUARTUS逻辑工程文件,逻辑工程软件版本为 Quartus II 10.1 (32-Bit)
timescale 1ns/100ps
module love_heart(
clk,
resetb,
key_in_a,
key_in_b,
led_out_b,
led_out_r,
led_out_g
);
input clk;
input resetb;
input key_in_a;
input key_in_b;
output[23:0] led_out_b;
output[23:0] led_out_r;
output[23:0] led_out_g;
reg[23:0] led_out_b;
reg[23:0] led_out_r;
reg[23:0] led_out_g;
//*****************************led_counter*********************************
reg[31:0] led_counter;
always@(posedge clk or negedge resetb)
begin
if (!resetb) led_counter <=0;
else led_counter <= led_counter +1'b1;
end
//*********************led_out_b**********************************
always@(posedge clk or negedge resetb)
begin
if (!resetb) led_out_b <=24'hfffffff;
else
case(led_counter[28:25])
4'h1: led_out_b <=24'h0000000;
4'h2: led_out_b <=24'hfffffff;
4'h7: led_out_b <=24'h0000000;
4'h8: led_out_b <=24'hfffffff;
4'h9: led_out_b <=24'h0000000;
4'ha: led_out_b <=24'hfffffff;
4'hb: led_out_b <=24'hfffffff;
4'hc: led_out_b <=24'hfffffff;
4'hd: led_out_b <=24'h0000000;
4'he: led_out_b <=24'hfffffff;
default: led_out_b <= 24'hfffffff;
endcase
end
//*********************led_out_r**********************************
always@(posedge clk or negedge resetb)
begin
if (!resetb) led_out_r <=24'hfffffff;
else
case(led_counter[28:25])
4'h3: led_out_r <=24'h0000000;
4'h4: led_out_r <=24'hfffffff;
4'h7: led_out_r <=24'h0000000;
4'h8: led_out_r <=24'hfff