内存的原理和时序(SDRAM、DDR、DDR-Ⅱ、Rambus_DRAM) 内存的原理和时序(SDRAM、DDR、DDR-Ⅱ、Rambus_DRAM) 内存的原理和时序(SDRAM、DDR、DDR-Ⅱ、Rambus_DRAM)

一篇很好的有关动态存储器（DRAM）的原理性文档，非常适合作为DRAM技术的入门文档。

• Ultra-low-voltage core and I/O power supplies • Frequency range – 933–10 MHz (data rate range: 1866–20 Mb/s/pin) • 8n prefetch DDR architecture • 8 internal banks for concurrent operation • Multiplexed, double data rate, command/address inputs; commands entered on each CK_t/CK_c edge • Bidirectional/differential data strobe per byte of data (DQS_t/DQS_c) • Programmable READ and WRITE latencies (RL/WL) • Burst length: 8 • Per-bank refresh for concurrent operation • Temperature-compensated self refresh (TCSR) • Partial-array self refresh (PASR) • Deep power-down mode (DPD) • Selectable output drive strength (DS) • Clock-stop capability • On-die termination (ODT) • RoHS-compliant, “green” packaging