第一章 Xilinx FPGA发展和应用 第二章 Xilinx FPGA时钟资源详述 第三章 Block RAM 核的功能简介和应用说明 第四章 TEMAC核的功能和应用介绍 第五章 LVDS技术规范及其应用 第六章 Xilinx DDR3存储器接口解决方案

XILINX fpga实现CNN，在硬件中实现神经网络，包括verilog语言、C语言

Xilinx Spartan-6 6L 全系列原理图库+PCB封装库（AD集成库）.IntLib后缀文件，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，集成库型号列表如下： Library Component Count : 454 Name Description ---------------------------------------------------------------------------------------------------- XC6SLX100-2CSG484C Spartan-6 LX 1.2V FPGA, 338 User I/Os, 484-Ball Chip-Scale BGA (0.8mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free XC6SLX100-2CSG484I Spartan-6 LX 1.2V FPGA, 338 User I/Os, 484-Ball Chip-Scale BGA (0.8mm Pitch), Speed Grade 2, Industrial Grade, Pb-Free XC6SLX100-2FG484C Spartan-6 LX 1.2V FPGA, 326 User I/Os, 484-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade XC6SLX100-2FG484I Spartan-6 LX 1.2V FPGA, 326 User I/Os, 484-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Industrial Grade XC6SLX100-2FG676C Spartan-6 LX 1.2V FPGA, 480 User I/Os, 676-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade XC6SLX100-2FG676I Spartan-6 LX 1.2V FPGA, 480 User I/Os, 676-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Industrial Grade XC6SLX100-2FGG484C Spartan-6 LX 1.2V FPGA, 326 User I/Os, 484-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free XC6SLX100-2FGG484I Spartan-6 LX 1.2V FPGA, 326 User I/Os, 484-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Industrial Grade, Pb-Free XC6SLX100-2FGG676C Spartan-6 LX 1.2V FPGA, 480 User I/Os, 676-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Commercial Grade, Pb-Free XC6SLX100-2FGG676I Spartan-6 LX 1.2V FPGA, 480 User I/Os, 676-Ball Fine-Pitch BGA (1.0mm Pitch), Speed Grade 2, Industrial Grade, Pb-Free XC6SLX100-3CSG484C Spartan-6 LX 1.2V FPGA, 338 User I/Os, 484-Ball Chip-Scale BGA (0.8mm Pitch), Speed Grade 3, Commercial Grade, Pb-Free XC6SLX100-3CSG484I Spartan-6 LX 1.2V FPGA, 338 User I/Os, 484-Ball Chip-Scale BGA (0.8mm Pitch), Speed Grade 3, Industrial Grade, Pb-Free XC6SLX100-3FG484C Spartan-6 LX 1.2V FPGA, 326 User I/Os, 484-Ball Fine-Pitch BGA (1.0m

Xilinx Spartan-3 3A 3E 3L 全系列原理图库+PCB封装库（AD集成库）.IntLib后缀文件，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，集成库型号列表如下： Library Component Count : 174 Name Description ---------------------------------------------------------------------------------------------------- XC3S1000-4FG320C Spartan-3 1.2V FPGA, 221 User I/Os, 320-Ball FBGA, Standard Performance, Commercial Grade XC3S1000-4FG320I Spartan-3 1.2V FPGA, 221 User I/Os, 320-Ball FBGA, Standard Performance, Industrial Grade XC3S1000-4FG456C Spartan-3 1.2V FPGA, 333 User I/Os, 456-Ball FBGA, Standard Performance, Commercial Grade XC3S1000-4FG456I Spartan-3 1.2V FPGA, 333 User I/Os, 456-Ball FBGA, Standard Performance, Industrial Grade XC3S1000-4FG676C Spartan-3 1.2V FPGA, 391 User I/Os, 676-Ball FBGA, Standard Performance, Commercial Grade XC3S1000-4FG676I Spartan-3 1.2V FPGA, 391 User I/Os, 676-Ball FBGA, Standard Performance, Industrial Grade XC3S1000-4FGG320C Spartan-3 1.2V FPGA, 221 User I/Os, 320-Ball FBGA, Standard Performance, Commercial Grade, Pb-Free XC3S1000-4FGG320I Spartan-3 1.2V FPGA, 221 User I/Os, 320-Ball FBGA, Standard Performance, Industrial Grade, Pb-Free XC3S1000-4FGG456C Spartan-3 1.2V FPGA, 333 User I/Os, 456-Ball FBGA, Standard Performance, Commercial Grade, Pb-Free XC3S1000-4FGG456I Spartan-3 1.2V FPGA, 333 User I/Os, 456-Ball FBGA, Standard Performance, Industrial Grade, Pb-Free XC3S1000-4FGG676C Spartan-3 1.2V FPGA, 391 User I/Os, 676-Ball FBGA, Standard Performance, Commercial Grade, Pb-Free XC3S1000-4FGG676I Spartan-3 1.2V FPGA, 391 User I/Os, 676-Ball FBGA, Standard Performance, Industrial Grade, Pb-Free XC3S1000-4FT256C Spartan-3 1.2V FPGA, 173 User I/Os, 256-Ball FTBGA, Standard Performance, Commercial Grade XC3S1000-4FT256I Spartan-3 1.2V FPGA, 173 User I/Os, 256-Ball FTBGA, Standard Performance, Industrial Grade XC3S1000-4FTG256C Spartan-3 1.2V FPGA, 173 User I/Os, 256-Ball FTBGA, Standard Performance, Commercial Grade, Pb-Fre

Xilinx cpld XC9500 XC9500XV 全系列原理图库+PCB封装库（AD集成库）.IntLib后缀文件，拆分后文件为PcbLib+SchLib格式，Altium Designer原理图库+PCB封装库，集成库型号列表如下： Library Component Count : 208 Name Description ---------------------------------------------------------------------------------------------------- XC95108-10PC84C XC9500 5V, 108 Macrocell CPLD, 69 User I/Os, 84-Pin PLCC, Commercial Grade XC95108-10PC84I XC9500 5V, 108 Macrocell CPLD, 69 User I/Os, 84-Pin PLCC, Industrial Grade XC95108-10PCG84C XC9500 5V, 108 Macrocell CPLD, 69 User I/Os, 84-Pin PLCC, Commercial Grade, Pb-Free XC95108-10PCG84I XC9500 5V, 108 Macrocell CPLD, 69 User I/Os, 84-Pin PLCC, Industrial Grade, Pb-Free XC95108-10PQ100C XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin PQFP, Commercial Grade XC95108-10PQ100I XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin PQFP, Industrial Grade XC95108-10PQ160C XC9500 5V, 108 Macrocell CPLD, 108 User I/Os, 160-Pin PQFP, Commercial Grade XC95108-10PQ160I XC9500 5V, 108 Macrocell CPLD, 108 User I/Os, 160-Pin PQFP, Industrial Grade XC95108-10PQG100C XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin PQFP, Commercial Grade, Pb-Free XC95108-10PQG100I XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin PQFP, Industrial Grade, Pb-Free XC95108-10PQG160C XC9500 5V, 108 Macrocell CPLD, 108 User I/Os, 160-Pin PQFP, Commercial Grade, Pb-Free XC95108-10PQG160I XC9500 5V, 108 Macrocell CPLD, 108 User I/Os, 160-Pin PQFP, Industrial Grade, Pb-Free XC95108-10TQ100C XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin TQFP, Commercial Grade XC95108-10TQ100I XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin TQFP, Industrial Grade XC95108-10TQG100C XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin TQFP, Commercial Grade, Pb-Free XC95108-10TQG100I XC9500 5V, 108 Macrocell CPLD, 81 User I/Os, 100-Pin TQFP, Industrial Grade, Pb-Free XC95108-15PC84C XC9500 5V, 108 Macrocell CPLD, 69 User I/Os, 84-Pin PLCC, Commercial Grade XC95108-15

本书详细讲解了Xilinx MPSoC的设计方法，全英文版，还原最纯真的英文释义，是一本很好的学习参考书。

Xilinx FPGA SPI FLASH外挂FLASH启动设置，步骤详细，每步骤都有截图，如何生成MCS文件，如何匹配所使用的FLASH型号，如何通过SPI加载MCS文件，非常详细

XIlinx Video On Screen Display（OSD）模块用户手册

关于xilinx spartan6系列FPGA的HPI使用例程，亲测可用

在Xilinx FPGA中通过AXI接口逻辑，实现4个独立的DDR4读写通道，通道数可由参数配置，完成对DDR4的控制，上传为完整工程，开发环境为Vivado2018.2，已经上板验证。