2010_MSC SOFTWARE中国用户大会论文集

Microsoft iSCSI Software Target 3.3 官方版本,WIN2008 64位,做网络存储用哦.

IBM Rational Software Architect（RSA) 9.0破解文件 解压后将jar包复制到\IBMIMShared\plugins目录，覆盖原文件。

simulation_and_software_radio_for_mobile_communications一书电子版和随书光盘附带源程序 matlab学习用

RF and Digital Signal Processing for Software-Defined Radio: A Multi-Standard Multi-Mode Approach by Tony J. Rouphael RF and Digital Signal Processing for Software-Defined Radio: A Multi-Standard Multi-Mode Approach By Tony J. Rouphael Publisher: Newnes Number Of Pages: 424 Publication Date: 2008-11-19 ISBN-10 / ASIN: 0750682108 ISBN-13 / EAN: 9780750682107 Binding: Paperback Product Description: Software-defined radio (SDR) is the hottest area of RF/wireless design, and this title describes SDR concepts, theory, and design principles from the perspective of the signal processing (both on transmission and reception) performed by a SDR system. After an introductory overview of essential SDR concepts, this book examines waveform creation, analog signal processing, digital signal processing, data conversion, phase-locked loops, SDR algorithms, and SDR hardware design. The various trade-offs at each of these design stages are discussed in detail. *Offers readers a powerful set of analytical and design tools *Details real world designs *Comprehensive coverage makes this a must have in the RF/Wireless industry

Software and systems engineering — Software testing Part5：关键字驱动测试 国际软件测试标准第五部分

Two-dimensional Phase Unwrapping: Theory, Algorithms, and Software一书的源代码

英文版的汽车软件工程-原理.过程.方法.工具，原汁原味。

Software Engineering, 8th edition, Ian Sommerville 2006 全英文PDF版课件 第二版

Petrify is a tool for the synthesis of bounded Petri nets and logic synthesis of asynchronous controllers. Petrify initially performs a token flow analysis of the Petri net and produces a finite transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfil the conditions required to obtain a Petri net with bisimilar or trace-equivalent behavior. Some properties for the synthesized Petri net can be imposed (e.g. free-choice, uniquechoice, pure, state-machine decomposable, etc.). Additionally, petrify can interpret the Petri net as a Signal Transition Graph (STG), in which events represent rising/falling transitions of digital signals. From an STG, petrify can synthesize a speed-independent circuit by solving the problems of state encoding, logic synthesis, logic decomposition and technology mapping onto a gate library. Petrify can also synthesize circuit under timing assumptions specified by the designer or automatically generated by the tool. Petrify reads the input description from stdin and writes the resulting STG to stdout unless otherwise specified