FIFO full_adder SPI接口 分頻器等9个VHDL设计源码Quartus工程文件, Quartus软件版本9.0,可以做为你的学习设计参考。
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.std_logic_arith.all;
entity spi_in is
port(
sck_in:in std_logic;
mosi:in std_logic;--收
miso:out std_logic;--发
data_out:out std_logic_vector(7 downto 0)
);
end spi_in;
architecture spi_behave of spi_in is
signal gain_data:std_logic_vector(7 downto 0);
signal num:integer range 0 to 9;
begin
process(sck_in)
begin
if(sck_in'event and sck_in='1')then
if(num=9)then
num<=0;
else
num0 and num<9)then
gain_data(9-num)<=mosi;
else
data_out<=gain_data;
end if;
end process;
end spi_behave;