This paper presents power management guidelines for PCI Express links on Intel-based Mobile platforms. It
describes the mapping from platform sleeping states and device power states to link power states, including the
procedure to support Mobile-specific S1/POS and CPU C3/C4 scenarios. Device and platform power saving
opportunities are identified for each link power state. L1 entry policy is also recommended to optimize device power.
Several power optimization techniques are described, including minimizing flow control updates and
acknowledgement packets to improve bandwidth efficiency, and pipelining packets to increase opportunities for active
state link power management. These power management guidelines enable architectural innovation to achieve
power-optimized interconnect performance.
2022-12-20 00:51:35
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PCIe
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