施耐德一些典型的编程技巧，学习一下非常不错的

MFC中Slider Control 使用简例

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扫描完整版 例学VBA：EXCEL ACCESS POWERPOINT中的VBA高效应用

使用ST新库Low-layer(LL)开发的串口1的DMA闲时中断接收+DMA发送数据配置例程,主函数会一直usart1会500ms用普通方式按1字节1字节发送数据,当串口1接收到数据IDLE中断后,会用DMA方式将接收到数据发送出去,方便串口助手回环测试

电路题解400例及学习考研指南 。。。。。。。。。。。。。。

介绍了模拟退火算法在背包问题中的应用步骤，以及程序实现方法。

李立宗《计算机视觉40例》PPT课件：第3章

这是从外网好不容易找到的，上传与大家共享，不要积分随便下！我也是下载的，不是自己发明的，如果再去要下载积分，人品还不至于这么差！ 里面有加密的，官方说明是这样的：There are two encrypted verilog files in the "DE2_70_TV_PIP" demonstraction. If users want to modify this demonstration and re-compile the project, please perform the following steps: 1.Use Notepad or other text edit software to open the file "Teraisc_license.dat", which is located in the "DE2_70_demonstrations/License for encrypted IP" folder of the DE2-70 System CD-ROM. 2. The license contains the FEATURE lines required to license the IP Cores as shown below FEATURE 535C_0009 alterad 9999.12 permanent uncounted D702CF471AC0 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="0F45 927A 00F9 DBF3 3AAB D703 4F3D 2406 B374 \ 0E5C 87A1 34BA 10C6 0C08 E554 183B BD2D B79D D64E 3F98 393E \ 94FB F798 07B8 C334 C8B6 D1E4 36F5 67D5 1690" FEATURE 535C_000A alterad 9999.12 permanent uncounted F7FD875F1A28 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="1834 5F1A 9CE6 15FD 9246 A640 66FE 918D 1091 \ A2D0 7DF8 7584 0E78 3732 1F48 0B24 3A92 870A EDAA F6F0 2145 \ 3098 5631 C5E1 4DC2 B14D C81A D30D 5518 63D0" 3.Open your Quartus II license.dat file in a text editor. 4.Copy the all the contents of the Terasic_license.dat and paste it at the end of your Quartus II license file. (Note: Do not delete any FEATURE lines from the Quartus II license file. Doing so will result in a non-usable license file.) 5.Open the "DE2_70_TV_PIP" project from Quartus II and compile this project. 6.After compilation is completed, it will generate a sof file named "DE2_70_TV_PIP_time_limited.sof" 7.Load this sof file into the FPGA and the demonstration will have at most one hour to be modified. In another words, the VGA output will be turned off after one hour. If users want to know more information about this demonstration, please contact us at support@terasic.com.

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