附安装教程：https://blog.csdn.net/xuexiaokkk/article/details/49818443

数字计数器+Verilog代码+仿真testbench+word版本+课程设计+实验

设计了一个双口RAM，数据口使用inout进行处理，testbench里对数据口进行了仿真，仿真结果已经通过modelsim

I will first introduce the necessary concepts and tools of verification, then I'll describe a process for planning and carrying out an effective functional verification of a design. I will also introduce the concept of coverage models that can be used in a coveragedriven verification process. It will be necessary to cover some VHDL and Verilog language semantics that are often overlooked or oversimplified in textbooks intent on describing the synthesizeable subset. These unfamiliar semantics become important in understanding what makes a wellimplemented and robust testbench and in providing the necessary control and monitor features. Once these new semantics are understood in a familiar language, the same semantics are presented in new verification-oriented languages. I will also present techniques for applying stimulus and monitoring the response of a design, by abstracting the physical-level transac-tions into high-level procedures using bus-functional models. The architecture of testbenches built around these bus-functional models is important to create a layer of abstraction relevant to the function being verified and to minimize development and maintenance effort. I also show some strategies for making testbenches selfchecking. Creating random testbenches involves more than calling the random() function in whatever language is used to implement them. I will show how random stimulus generators, built on top of busfunctional models, can be architected and designed to be able to produce the desired stimulus patterns. Random generators must be easily externally constrained to increase the likelihood that a set of interesting patterns will be generated. Behavioral modeling is another important concept presented in this book. It is used to parallelize the implementation and verification of a design and to perform more efficient simulations. For many, behavioral modeling is synonymous with synthesizeable or RTL modeling. In this book, the term "behavioral" is used to

网上找来编写testbench的一些总结，对初学者非常有用(基于verilog)

借鉴UVM的测试方法，在tb中将初始数据和结果数据写入txt文件，处理完成后，读出来，进行逐一对比，并打印结果。无需肉眼一一对比，将结果用计算机自动对比，减少人工工作量，提高了准确率。

虽然简单，但是流程很全，教你一步步实现modelsim仿真，很适合新手！

大量verilog实例，源码及其测试文件testbench，通过验证。对初学者有极大帮助.

一本比较好的FPGA testbench编写英文书籍，对于初学者可以学习。英文资料相对中文资料讲的通俗易懂。

vivado中FFT核的调用配置及Verilog HDL 版本的testbench.v文件