基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从 ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire osd_hs; wire osd_vs; wire osd_de; wire[7:0] osd_r; wire[7:0] osd_g; wire[7:0] osd_b; assign vga_out_hs = osd_hs; assign vga_out_vs = osd_vs; assign vga_out_r = osd_r[7:3]; //discard low bit data assign vga_out_g = osd_g[7:2]; //discard low bit data assign vga_out_b = osd_b[7:3]; //discard low bit data //generate video pixel clock video_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ) ); color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b

读取SD卡中的BMP图片并通过VGA LCD屏显示的Verilog逻辑源码Quartus工程文件+文档说明，实验将SD卡里的BMP图片读出，写入到外部存储器，再通过 VGA、LCD 等显示，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16 ; //external memory user interface data width parameter ADDR_BITS = 24 ; //external memory user interface address width parameter BUSRT_BITS = 10 ; //external memory user interface burst width wire

FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16; //external memory user interface data width parameter ADDR_BITS = 24; //external memory user interface address width p

FPGA读取AD芯片AD9238数据并波形显示例程Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire grid_hs; wire grid_vs; wire grid_de; wire[7:0] grid_r; wire[7:0] grid_g; wire[7:0] grid_b; wire wave0_hs; wire wave0_vs; wire wave0_de; wire[7:0] wave0_r; wire[7:0] wave0_g; wire[7:0] wave0_b; wire wave1_hs; wire wave1_vs; wire wave1_de; wire[7:0] wave1_r; wire[7:0] wave1_g; wire[7:0] wave1_b; wire adc_clk; wire adc0_buf_wr; wire[10:0] adc0_buf_addr; wire[7:0] adc0_buf_data; wire adc1_buf_wr; wir

FPGA读取模数转换芯片AD7606数据并波形显示例程Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, input[15:0] ad7606_data, //ad7606 data input ad7606_busy, //ad7606 busy input ad7606_first_data, //ad7606 first data output[2:0] ad7606_os, //ad7606 output ad7606_cs, //ad7606 AD cs output ad7606_rd, //ad7606 AD data read output ad7606_reset, //ad7606 AD reset output ad7606_convstab, //ad7606 AD convert start //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire grid_hs; wire grid_vs; wire grid_de; wire[7:0] grid_r; wire[7:0] grid_g; wire[7:0] grid_b; wire wave0_hs; wire wave0_vs; wire wave0_de; wire[7:0] wave0_r; wire[7:0] wave0_g; wire[7:0] wave0_b; wire wave1_hs; wire wave1_vs; wire

基于FPGA设计的 AD9708 +AD9280 ADDA转换测试Verilog逻辑源码Quartus工程文件+文档说明，DA芯片选用AD公司推出的AD9708，AD芯片选用AD9280，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, //adc input[7:0] ad9280_data, output ad9280_clk, //dac output[7:0] ad9708_data, output ad9708_clk, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire grid_hs; wire grid_vs; wire grid_de; wire[7:0] grid_r; wire[7:0] grid_g; wire[7:0] grid_b; wire wave0_hs; wire wave0_vs; wire wave0_de; wire[7:0] wave0_r; wire[7:0] wave0_g; wire[7:0] wave0_b; wire adc_clk; wire adc0_buf_wr; wire[10:0] adc0_buf_addr; wire[7:0] adc0_buf_data; wire dac_clk; wire[7:0] dac_data; reg[8:0] rom_addr; assign vga_out_hs = wave0_hs; assign vga_out_vs = wave0_vs; assign vga_out_r = wave0_r[7:3]; //discard low bit data assign vga_out_g

基于FPGA设计的不同频率PWM蜂鸣器控制实验Verilog逻辑源码Quartus工程文件+文档说明，用 PWM 控制蜂鸣器，用丌同频率的 pwm 让蜂鸣器发出丌一样的响声，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module buzzer_pwm_test( input clk, input rst_n, input key1, output buzzer ); parameter IDLE = 0; parameter BUZZER = 1; wire button_negedge; wire pwm_out; reg[31:0] period; reg[31:0] duty; reg[3:0] state; reg[31:0] timer; assign buzzer = ~(pwm_out & (state == BUZZER));//buzzer low active always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin period <= 32'd0; timer <= 32'd0; duty <= 32'd429496729; state <= IDLE; end else case(state) IDLE: begin if(button_negedge) begin period <= 32'd8590; //The pwm step value state <= BUZZER; duty = 32'd12_499_999) //buzzer effictive time 250ms begin state <= IDLE; timer <= 32'd0; end else begin timer <= timer + 32'd1; end end default: begin state <= IDLE; end endcase end ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key1), .button_posedge (), .button_negedge (button_negedge), .button_out () ); ax_pwm# ( .N(32) ) ax_pwm_m0( .clk (clk), .rst (~rst_n), .period (period), .duty (duty), .pwm_out (pwm_out) ); endmodule

FPGA设计串口收发实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module uart_test( input clk, input rst_n, input uart_rx, output uart_tx ); parameter CLK_FRE = 50;//Mhz localparam IDLE = 0; localparam SEND = 1; //send HELLO ALINX\r\n localparam WAIT = 2; //wait 1 second and send uart received data reg[7:0] tx_data; reg[7:0] tx_str; reg tx_data_valid; wire tx_data_ready; reg[7:0] tx_cnt; wire[7:0] rx_data; wire rx_data_valid; wire rx_data_ready; reg[31:0] wait_cnt; reg[3:0] state; assign rx_data_ready = 1'b1;//always can receive data, //if HELLO ALINX\r\n is being sent, the received data is discarded always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin wait_cnt <= 32'd0; tx_data <= 8'd0; state <= IDLE; tx_cnt <= 8'd0; tx_data_valid <= 1'b0; end else case(state) IDLE: state <= SEND; SEND: begin wait_cnt <= 32'd0; tx_data <= tx_str; if(tx_data_valid == 1'b1 && tx_data_ready == 1'b1 && tx_cnt < 8'd12)//Send 12 bytes data begin tx_cnt <= tx_cnt + 8'd1; //Send data counter end else if(tx_data_valid && tx_data_ready)//last byte sent is complete begin tx_cnt <= 8'd0; tx_data_valid <= 1'b0; state <= WAIT; end else if(~tx_data_valid) begin tx_data_valid <= 1'b1; end end WAIT: begin wait_cnt <= wait_cnt + 32'd1; if(rx_data_valid == 1'b1) begin tx_data_valid <= 1'b1; tx_data <= rx_data; // send uart received data end else if(tx_data_valid && tx_data_ready) begin tx_data_valid <= 1

FPGA 读写rtc_ds1302实时时钟的Verilog逻辑源码Quartus工程文件+文档说明，RTC芯片型号ds1302，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( //sys input clk, input rst_n, output rtc_sclk, output rtc_ce, inout rtc_data, output [5:0] seg_sel, output [7:0] seg_data ); wire[7:0] read_second; wire[7:0] read_minute; wire[7:0] read_hour; wire[7:0] read_date; wire[7:0] read_month; wire[7:0] read_week; wire[7:0] read_year; seg_bcd seg_bcd_m0( .clk (clk), .rst_n (rst_n), .seg_sel (seg_sel), .seg_data (seg_data), .seg_bcd ({read_hour,read_minute,read_second}) ); ds1302_test ds1302_test_m0( .rst (~rst_n), .clk (clk), .ds1302_ce (rtc_ce), .ds1302_sclk (rtc_sclk), .ds1302_io (rtc_data), .read_second (read_second), .read_minute (read_minute), .read_hour (read_hour), .read_date (read_date), .read_month (read_month), .read_week (read_week), .read_year (read_year) ); endmodule

FPGA 读写i2c_eeprom_Verilog逻辑源码Quartus工程文件+文档说明，EEPROM 型号24LC04,，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module i2c_eeprom_test( input clk, input rst_n, input key1, inout i2c_sda, inout i2c_scl, output [5:0] seg_sel, output [7:0] seg_data ); localparam S_IDLE = 0; localparam S_READ = 1; localparam S_WAIT = 2; localparam S_WRITE = 3; reg[3:0] state; wire button_negedge; reg[7:0] read_data; reg[31:0] timer; wire scl_pad_i; wire scl_pad_o; wire scl_padoen_o; wire sda_pad_i; wire sda_pad_o; wire sda_padoen_o; reg[ 7:0] i2c_slave_dev_addr; reg[15:0] i2c_slave_reg_addr; reg[ 7:0] i2c_write_data; reg i2c_read_req; wire i2c_read_req_ack; reg i2c_write_req; wire i2c_write_req_ack; wire[7:0] i2c_read_data; ax_debounce ax_debounce_m0 ( .clk (clk), .rst (~rst_n), .button_in (key1), .button_posedge (), .button_negedge (button_negedge), .button_out () ); wire[6:0] seg_data_0; seg_decoder seg_decoder_m0( .bin_data (read_data[3:0]), .seg_data (seg_data_0) ); wire[6:0] seg_data_1; seg_decoder seg_decoder_m1( .bin_data (read_data[7:4]), .seg_data (seg_data_1) ); seg_scan seg_scan_m0( .clk (clk), .rst_n (rst_n), .seg_sel (seg_sel), .seg_data (seg_data), .seg_data_0 ({1'b1,7'b1111_111}), .seg_data_1 ({1'b1,7'b1111_111}), .seg_data_2 ({1'b1,7'b1111_111}), .seg_data_3 ({1'b1,7'b1111_111}), .seg_data_4 ({1'b1,seg_data_1}), .seg_data_5 ({1'b1,seg_data_0}) ); always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin state <= S_IDLE; i2c_write_req <= 1'b0; read_data <= 8'h00; timer <= 32'd0; i2c_write_data <= 8'd0; i2c_slave_reg_addr <= 16'd0; i2c_slave_dev_addr <= 8'ha0;//1010 000 0(default address ‘000’ write operation) i2c_read_req <= 1'b0; en