--rtl 这是源代码 --sim 这是modelsim仿真目录 已经验证，可以实现异步FIFO 两级寄存器实现读写指针的同步，地址采用格雷码形式防止亚稳态。异步FIFO的源码，个人觉得不易理解，故上传本人最近写的源码，与大家一起分享

简易异步FIFO代码及testbench，满足基本FIFO要求，简单实用

异步FIFO的空、满、半满、将空、将满标志都有包含，代码通过modelsim验证

这是一个异步FIFO的完全代码实现的modelsim工程，并附有参考论文。 仅作为参考，当然其中也有很多不足，希望批评指教，相互学习。

异步FIFO，跨时钟通信必备，完整代码verilog版本.......

FIFOs are often used to safely pass data from one clock domain to another asynchronous clock domain. Using a FIFO to pass data from one clock domain to another clock domain requires multi-asynchronous clock design techniques. There are many ways to design a FIFO wrong. There are many ways to design a FIFO right but still make it difficult to properly synthesize and analyze the design. This paper will detail one method that is used to design, synthesize and analyze a safe FIFO between different clock domains using Gray code pointers that are synchronized into a different clock domain before testing for "FIFO full" or "FIFO empty" conditions. The fully coded, synthesized and analyzed RTL Verilog model (FIFO Style #1) is included.

压缩包里是异步FIFO的IP核。。。。。。。。。。。。。。。。。。。。。。