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The Verilog® Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers.

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modbus 官方标准从机程序，只要简单的更改各个数组，就能实现modbus 各个功能码的功能

SAP BW310官方标准教程，关于SAP BI的入门教程

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DisplayPort（DP）是目前正在兴起的音视频传输接口，本文档是目前最新的1.2a版本官方标准，支持MST传输技术。