基于FPGA的时分秒实验
实现如下功能:
六个数码管显示,如22:49:25
(Quartus II 7.0 )
部分代码:
Library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
--//=======================================
entity hourmins is
port(clk1000:IN STD_LOGIC;--时钟1000
RST:IN STD_LOGIC;--复位
DEL:buffer STD_LOGIC_VECTOR(2 DOWNTO 0);--位选
led7:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)--数码管
);
END hourmins;
--//=======================================
architecture behave of hourmins is
-------------------------------------------------------
signal count_1s:integer range 0 to 59;--1S计数
signal secondhigh:integer range 0 to 5;--数码管显示十位
signal secondlow:integer range 0 to 9;--数码管显示个位
-------------------------------------------------------
1