This book has one large omission: assertions and formal verification. It is not that they are not important. SystemVerilog includes constructs and semantics for writing assertions and coverage properties using temporal expressions. Formal verification is already an effective methodology for verifying certain classes of designs. It is simply a matter of drawing a line somewhere. There are already books on assertions1 or formal verification. This book focuses on the bread-and-butter of verification for the foreseeable future: dynamic functional verification using testbenches 以下的资源也很不错, 加减可以看一下o 使用C++制作3D动画人物-100%提供源码 http://download.csdn.net/source/2255453 http://hqioan.download.csdn.net/

I will first introduce the necessary concepts and tools of verification, then I'll describe a process for planning and carrying out an effective functional verification of a design. I will also introduce the concept of coverage models that can be used in a coveragedriven verification process. It will be necessary to cover some VHDL and Verilog language semantics that are often overlooked or oversimplified in textbooks intent on describing the synthesizeable subset. These unfamiliar semantics become important in understanding what makes a wellimplemented and robust testbench and in providing the necessary control and monitor features. Once these new semantics are understood in a familiar language, the same semantics are presented in new verification-oriented languages. I will also present techniques for applying stimulus and monitoring the response of a design, by abstracting the physical-level transac-tions into high-level procedures using bus-functional models. The architecture of testbenches built around these bus-functional models is important to create a layer of abstraction relevant to the function being verified and to minimize development and maintenance effort. I also show some strategies for making testbenches selfchecking. Creating random testbenches involves more than calling the random() function in whatever language is used to implement them. I will show how random stimulus generators, built on top of busfunctional models, can be architected and designed to be able to produce the desired stimulus patterns. Random generators must be easily externally constrained to increase the likelihood that a set of interesting patterns will be generated. Behavioral modeling is another important concept presented in this book. It is used to parallelize the implementation and verification of a design and to perform more efficient simulations. For many, behavioral modeling is synonymous with synthesizeable or RTL modeling. In this book, the term "behavioral" is used to

LabVIEW开发FPGA的视频资料，中文字幕。更多内容登录www.bjcyck.com

技术写作第十一版，相比以前版本，有了更多细节上的讲解。

讲technical writing的书, 很全面.

writing-your-first-riscv-simulator 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料

Academic Writing for Graduate Students-Essential Tasks and Skills

writing-a-simple-operating-system-from-scratch 从零开始写一个简单的操作系统 该代码是我在学习Nick Blundel的PDF教程时按照教程编写的，分享出来，供OS爱好者参考。 原，作者：英国伯明翰大学计算机学院教师 Nick Blundell。 我的， 编译机： CentOS Linux 6.6 i386 [root@nut32 ~]# uname -a Linux nut32.nutdomain 2.6.32-504.el6.i686 #1 SMP Wed Oct 15 03:02:07 UTC 2014 i686 i686 i386 GNU/Linux 编译环境： GNU ld version 2.20.51.0.2-5.43.el6 20100205 GCC 4.4.7 NASM version 2.07 测试内核环境： 虚拟机：QEM

Q Skills for Success Level 3 Reading and Writing.pdf！

Use this subroutine to define any complex, constitutive models for materials that cannot be modeled with the available ABAQUS material models.