本书详细讲解了Xilinx MPSoC的设计方法,全英文版,还原最纯真的英文释义,是一本很好的学习参考书。
2021-04-09 15:29:18 46.99MB FPGA Xilinx MPSoC
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例程源码,项目移植,硬件设计参考,图像处理,PCIE,AD采集等等
2021-04-03 18:03:18 1.22MB 开发板 黑金 UltraScale Zynq
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可重构异构MPSoC上无序执行的评估和权衡
2021-02-25 22:04:50 2.87MB 研究论文
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高效的软件/硬件代码签名对嵌入式系统提出了严峻的挑战。 本文提出了Codem,一种用于嵌入式系统的软件/硬件代码流,它将处理器和知识产权(IP)核心都建模为服务。 任务被视为抽象指令,可以将其调度到IP内核以自动并行执行。 为了指导热点功能的硬件实现,本文结合了一种新颖的基于热点的分析技术,以在仿真应用程序时观察热点功能。 此外,基于各种应用程序的热点,提出了一种自适应映射算法,将应用程序划分为多个软件/硬件任务。 我们使用经典的Sort应用程序测试基于配置文件的设计流程。 实验结果表明,Codem可以有效地帮助研究人员识别热点,并且还概述了将分析技术与最新的可重配置计算平台相结合以实现特定任务加速的新方向。
2021-02-25 22:03:59 917KB MPSoC; hardware service; hardware/software
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Efficient design of Multi-Processor System-On-Chip (MPSoC) requires early, fast and accurate performance estimation techniques. In this paper, we present new techniques based on fine-grained code analysis to estimate accurate performance during simulation of MPSoC Transaction Accurate Models. First, a GCC profiling tool is applied in the native simulation process. Based on the profiling result, an instruction analyzer of the target CPU architecture is proposed to analyze the cycle cost of C code
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Multi-processor system on chip (MPSoC) has been widely applied in embedded systems in the past decades. However, it has posed great challenges to efficiently design and implement a rapid prototype for diverse applications due to heterogeneous instruction set architectures (ISA), programming interfaces and software tool chains. In order to solve the problem, this paper proposes a novel high level architecture support for automatic out-of-order (OoO) task execution on FPGA based heterogeneous MPSoCs. The architecture support is composed of a hierarchical middleware with an automatic task level OoO parallel execution engine. Incorporated with a hierarchical OoO layer model, the middleware is able to identify the parallel regions and generate the sources codes automatically. Besides, a runtime middleware Task-Scoreboarding analyzes the inter-task data dependencies and automatically schedules and dispatches the tasks with parameter renaming techniques. The middleware has been verified by the prototype built on FPGA platform. Examples and a JPEG case study demonstrate that our model can largely ease the burden of programmers as well as uncover the task level parallelism.
2021-01-28 00:52:23 1.95MB MPSoC
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博客配套原码工程 https://blog.csdn.net/botao_li/article/details/86221390
2019-12-21 19:29:34 7.48MB zcu102 zynq emio mpsoc
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