存数(sw)指令的数据通路
M[ R[rs] + SignExt[imm16] ] ← R[rt] Example: sw rt, rs, imm16
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5
5
5
Rw
Ra
Rb
32 32-bit
Registers
Rs
Rt
Rt
Rd
RegDst
Ext
Mux
Mux
32
16
imm16
ALUSrc
ExtOp
Mux
MemtoReg
Clk
Data In
WrEn
32
Adr
Data
Memory
32
MemWr
ALU
RegDst=x, RegWr=0, ALUctr=add, ExtOp=1, ALUSrc=1, MemWr=1, MemtoReg=x
0
1
0
1
加兰色部分。才能向存储器存数
0
1
op
rs
rt
imm16
0
16
21
26
31
6 bits
16 bits
5 bits
5 bits
And here is the datapath for the store instruction.
The Register File, the ALU, and the Extender are the same as the datapath for the load instruction because the memory address has to be calculated the exact same way:
(a) Put the register selected by Rs onto bus A and sign extend the 16 bit immediate field.
(b) Then make the ALU (ALUctr) adds these two (busA and output of Extender) together.
The new thing we added here is busB extension (DataIn).
More specifically, in order to send the register selected by the Rt field (Rb of the register file) to data memory, we need to connect bus B to the data memory’s Data In bus.
Finally, the store instruction is the first instruction we encountered that does not do any register write at the end.
Therefore the control unit must make sure RegWr is zero for this instruction.
+2 = 64 min. (Y:44)
2022-04-10 21:09:08
4.02MB
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