Specifically, this book
deals in depth with the following issues:
• A methodology for simultaneous non-zero clock skew scheduling and design
of the topology of the clock distribution network. This methodology is
based on the pioneering works of Friedman [1] and Fishburn [2], and builds
on Linear Programming (LP) solution techniques. The non-zero clock skew
scheduling of circuits with level-sensitive latches and for multi-phase clock
signals is formulated as a LP problem. The simultaneous clock scheduling
and clock tree topology synthesis problem is formulated as a mixed-integer
linear programming problem that can be solved efficiently. The proposed
algorithms have been evaluated on a variety of benchmark and industrial
circuits and synchronous performance improvements of well above 60%
have been demonstrated.
• For those cases where reliable circuit operation and production yield are
the highest level priorities, an alternative problem formulation is developed.
This formulation is based on a quadratic (hence the QP—quadratic
programming) measure, or cost function, of the tolerance of a clock schedule
to parameter variations. A mathematical framework is presented for
solving the constrained and bounded QP problem. A constrained version
of the problem is iteratively solved using the Lagrange multipliers
method. As these research issues are topics of great practical importance
for input/output (I/O) interfacing and Intellectual Property (IP) blocks,
explicit clock delay and skew requirements are fully integrated into the
mathematical model described here.
The theoretical derivation of the limits on the improvements on the clock
period available through clock skew scheduling. The theoretical derivation
is performed by identifying the limits for three local data path topologies.
A methodology to mitigate the limitation of clock skew scheduling for a
reconvergent path system is presented. The methodology involves delay
insertion on some data paths of the reconvergent syst
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