思维导图详细解析SSD相关基础知识。 PCIe协议栈：Transaction Layer：事务层，Data Link Layer：数据链路层，Physical Layer：物理层解析； PCIe 数据包TLP（Transaction Layer Packet）详细解析； NVMe协议解析：SQ，CQ，DB； 主机读写SSD流程详解。

研华板卡EtherCAT的使用中文软硬件使用说明 通用板卡型号： PCI-1203/PCIE-1203 EtherCAT Master PCI 卡

88SE9215 R1.1 One-Lane PCIe 2.0 to Four-Port 6 Gbps SATA I_O.pdf

88SE9230 R1.1 Two-Lane PCIe 2.0 to Four-Port SATA 6 Gbps RAI.pdf

通俗易懂，从一：PCIE 接口介绍，二：PCIE 系统架构介绍，三：PCIE 设备枚举过程，四：PCIE 设备的配置空间，五：PCIE 协议的TLP介绍等五个方面对PCIE进行了介绍

PCIe5.0 规范V1.0 PCI Express® Base Specification Revision 5.0 Version 1.0 22 May 2019 Copyright © 2002-2019 PCI-SIG ® PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners. Contact PCI-SIG Membership Services for questions about membership in the PCI-SIG or to obtain the latest revision of this specification. Contact PCI-SIG Technical Support for technical questions about this specification. DISCLAIMER PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein. This PCI Specification is provided “as is” without any warranties of any kind, including any warranty of merchantability, non-infringement, fitness for any particular purpose, or any warranty otherwise arising out of any proposal, specification, or sample. PCI-SIG disclaims all liability for infringement of proprietary rights, relating to use of information in this specification. This document itself may not be modified in any way, including by removing the copyright notice or references to PCI-SIG. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted herein. PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG. All other product names are trademarks, registered trademarks, or servicemarks of their respective owners.

利用DriverStudio、DDK以及VC6.0联合开发工具,采用基于对象的C++语言,实现了 PCIE总线设备的WDM式驱动程序和应用程序即上位机的开发,以及上位机界面的数据速率显示功能。在Windows XP系统下,驱动程序能够稳定运行。通过实际的检验,数据采集系统的读、写速率可以达到1.3?1.5GB/S,较之其他的一些系统实现了较高的数据传输速率,但是仍有改进的空间。本课题的研究需要对Windows系统下驱动程序的模型以及驱动程序的结构组成有较为深入的了解,在本文中,PICE的驱动程序为DM式驱动程序,需要对WDM式驱动程序模型的特点有较全面的了解;同时需要熟悉应用程序与动程序进行通信的过程,熟悉应用程序界面的设计代码,熟悉如何使用面向对 象的C++语言来设计上位机界面中的各按钮,并将其与硬件设备的操作相对应。高速数据釆集系统将硬件A/D采集来的数据经过PCIE总线传输给应用程序的上位机,上位机通过计算显示数据的采集速率

NVMe最新协议版本

PCI_Express_Base_4.0.pdf

王齐老师的《PCI Express体系结构导读》能够让读者从宏观上了解并理解PCI Express体系结构，是国人在这方面写的很实用的一本书，结合在Xilinx 7系列FPGA中PCIe IP核中文手册的学习能够帮助加快PCIe的学习和开发应用。