采用verilog编写,这里是
USB核心的分层视图:
usb1_core
|
+ - usb_phy
| |
| + - usb_tx_phy
| |
| + - usb_rx_phy
|
+ - usb1_utmi_if
|
+ - usb1_pl
| |
| + - usb1_pd
| |
| + - usb1_pa
| |
| + - usb1_idma
| |
| + - usb1_pe
|
+ - usb1_ctrl
|
+ - usb1_rom1
|
+ - 2x generic_fifo_sc_a
|
+ - generic_dpram
1