TI TDA3X 芯片手册 TDA3x is an ADAS applications device based on enhanced OMAP™ architecture integrated on a 28-nm technology. TDA3x complements the TDA2x ADAS device family by using a common architecture, enabling scalability from entry to high performance for a broad range of applications. • The device family is targeted at ADAS applications including Front Camera, Intelligent Rear Camera, Radar and Mirror Replacement.

NVM_Express_Revision_1.3.pdf PCIE NVME协议规范，有兴趣的同学自行下载

PCIe SPEC

LXI Standard Revision 1.3 LXI 标准1.3版，英文原版

1. System Overview The MT6218B is a highly integrated single chip solution for GSM/GPRS phone. Based on 32 -bit ARM7EJ-STM RISC processor, MT6218B features not only high performance GPRS Class 12 MODEM but is also designed with support for the wireless multi-media applications, such as advanced display engine, hardware JPEG decoder, synthesis audio with 64-tone polyphony, digital audio playback, Java acceleration, MMS and etc. Additionally, MT6218B provides varieties of advanced interfaces for functionality extensions, like 8-port external memory interface, 3-port 8-bit parallel interface, NAND Flash, IrDA, USB and MMC/SD/MS/MS Pro. The typical application can be shown as Figure 1.

1. System Overview The MT6205B is a highly integrated baseband processor optimized specially for multi-media enabled GSM terminal. Combining the 32-bit ARM7TDMITM RISC processor core, proprietary low-power digital signal processor, user interface, radio control, audio codec, baseband codec, and other GSM specific analog and digital hardware, the MT6205B completes the best single-chip solution for GSM phone with multi-media function. The typical application can be shown as Figure 1.

PCI Express Base Specification Revision 2.0 协议规范

This specification defines a standardized NAND Flash device interface that provides the means for a system to be designed that supports a range of NAND Flash devices without direct design pre-association. The solution also provides the means for a system to seamlessly make use of new NAND devices that may not have existed at the time that the system was designed.

1. INTRODUCTION............................................................................................................... 46 1.1. A THIRD GENERATION I/O INTERCONNECT ................................................................... 46 1.2. PCI EXPRESS LINK......................................................................................................... 49 1.3. PCI EXPRESS FABRIC TOPOLOGY .................................................................................. 50 1.3.1. Root Complex........................................................................................................ 50 1.3.2. Endpoints .............................................................................................................. 51 1.3.3. Switch .................................................................................................................... 54 1.3.4. Root Complex Event Collector .............................................................................. 55 1.3.5. PCI Express to PCI/PCI-X Bridge........................................................................ 55 1.4. PCI EXPRESS FABRIC TOPOLOGY CONFIGURATION ....................................................... 55 1.5. PCI EXPRESS LAYERING OVERVIEW.............................................................................. 56 1.5.1. Transaction Layer ................................................................................................. 57 1.5.2. Data Link Layer .................................................................................................... 57 1.5.3. Physical Layer ...................................................................................................... 58 1.5.4. Layer Functions and Services............................................................................... 58 TRANSACTION LAYER SPECIFICATION ................................................................. 62 2.1. TRANSACTION LAYER OVERVIEW.................................................................................. 62 2.1.1. Address Spaces, Transaction Types, and Usage................................................... 63 2.1.2. Packet Format Overview ...................................................................................... 65 2.2. TRANSACTION LAYER PROTOCOL - PACKET DEFINITION............................................... 67 2.2.1. Common Packet Header Fields ............................................................................ 67 2.2.2. TLPs with Data Payloads - Rules ......................................................................... 70 2.2.3. TLP Digest Rules .................................................................................................. 74 2.2.4. Routing and Addressing Rules .............................................................................. 74 2.2.5. First/Last DW Byte Enables Rules........................................................................ 78 2.2.6. Transaction Descriptor ......................................................................................... 81 2.2.7. Memory, I/O, and Configuration Request Rules................................................... 87 2.2.8. Message Request Rules ......................................................................................... 94 2.2.9. Completion Rules ................................................................................................ 115 2.2.10. TLP Prefix Rules ................................................................................................. 118 2.3. HANDLING OF RECEIVED TLPS.................................................................................... 123 2.3.1. Request Handling Rules...................................................................................... 126 2.3.2. Completion Handling Rules................................................................................ 138 2.4. TRANSACTION ORDERING ............................................................................................ 142 2.4.1. Transaction Ordering Rules ............................................................................... 142 ......

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