这是目前能找到的最全最新的工具软件指导书。 英文版,对应这个网页 http://www.amazon.com/Digital-Design-Cadence-Synopsys-Tools/dp/0321547993/ref=sr_1_1?ie=UTF8&qid=1308240051&sr=8-1
2022-03-23 21:27:05 13.59MB Digital VLSI Chip Design
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TLSR8369 for Telink 2.4GHz RF System-On-Chip Solution TLSR8369
2022-02-25 22:24:17 2.67MB TLSR8369
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MENTOR最新的车载软件解决方案。MENTOR的工具链,软件包,系统,解决方案等的详细介绍。
2022-02-02 14:02:47 10.67MB MENTOR autosar
有助于快速找到CHIP的相关数据,因为CHIP是统计学中常用的量化数据,可以从中提炼很多有价值的信息,希望可以帮助各位。
2022-01-20 16:58:30 323B CHIP
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IC测试工程师必备书籍,主要介绍atpg,lbist,mbist,diagnose等知识,适合DFT工程师和ATE工程师。
2022-01-19 15:34:40 9.94MB DFT必备书籍
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Flip Chip既是一种芯片互连技术,又是一种理想的芯片粘接技术.早在30年前IBM公司已研发使用了这项技术。但直到近几年来,Flip-Chip已成为高端器件及高密度封装领域中经常采用的封装形式。
2022-01-18 11:37:28 81KB Flip-Chip 倒装焊芯片 文章 硬件设计
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Model-based Analysis of ChIP-Seq (MACS)
2021-12-30 12:10:05 292KB MACS
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磁盘检测工具,检测U盘设备的芯片型号的软件工具,可以自动查询读卡器、U盘、MP3/MP4、移动硬盘等的主控芯片型号、制造商、品牌等
2021-12-29 13:06:07 842KB chip 磁盘
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课设所涉及到的proteus文件和keil文件都在其中,下载即可用。功能:5位独立按键中断;LCD1602显示(年月日星期时分秒);DS1302时钟芯片;两路闹钟设置;AT89S52基本电路图。
2021-12-27 17:01:47 120KB C语言 Proteus Keil
Abstract On-chip interconnects are predicted to be a fundamental issue in designing multi-core chip multiprocessors (CMPs) and system-on-chip (SoC) architectures with numerous homogeneous and heterogeneous cores and functional blocks. To mitigate the interconnect crisis, one promising option is network-on-chip (NoC), where a general purpose on-chip interconnection network replaces the traditional design-specific global on-chip wiring by using switching fabrics or routers to connect IP cores or processing elements. Such packet-based communication networks have been gaining wide acceptance due to their scalability and have been proposed for future CMPs and SoC design. In this chapter, we study the combination of both three-dimensional integrated circuits and NoCs, since both are proposed as solutions to mitigate the interconnect scaling challenges. This chapter will start with a brief introduction on network-on-chip architecture and then discuss design space exploration for various network topologies in 3D NoC design, as well as different techniques on 3D on-chip router design. Finally, it describes a design example of using 3D NoC with memory stacked on multi-core CMPs.
2021-12-17 08:14:32 1.48MB Yuan Xie Narayanan Vijaykrishnan
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