赛灵思 Zynq UltraScale+MPSoC 开发板型号：ZCU102 的原理图
2021-07-22 14:57:37
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该文档是xilinx官网提供的KCU116 DXDesigner原理图的PDF版本。该文档是xcku5p参考开发板，其中包括系统启动、时钟、电源、PCIE、GPIO、DDR4、以太网、IIC等设计，为硬件设计者提供参考。
2021-07-20 16:40:33
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This manual is part of the safety documentation related to the Xilinx® Zynq® UltraScale+™
MPSoC and its purpose is to describe the use of the Zynq UltraScale+ MPSoC device in the
context of a safety-related system, specifying user responsibilities for installation and
operation of these devices in your safety systems to maintain the desired safety integrity
level.
This safety manual is written in compliance with the Automotive Safety Standard ISO-26262,
edition 2011/2012, also taking in account the guidance given by the Draft version of
ISO-26262 Part 11 available in April 2016 (Part 11, together with the complete Revision 2 of
ISO-26262 will be officially published in 2018).
2021-07-01 11:48:54
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Xilinx官方文档，讲的是UltraScale系列FPGA的存储器IPcore。主要有DDR3/DDR4,LPDDR3,QDR等存储器接口控制协议IPcore，相似于老版本vivado或ISE的MIG(Memory Interface Generator)，此文档的IPcore讲的IPcore本质上也是MIG
2021-06-10 10:50:32
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