该文档是xilinx官网提供的KCU116 DXDesigner原理图的PDF版本。该文档是xcku5p参考开发板，其中包括系统启动、时钟、电源、PCIE、GPIO、DDR4、以太网、IIC等设计，为硬件设计者提供参考。

ACU3EG Zynq UltraScale+ 核心板 黑金 原理图

Zynq UltraScale+ 开发板原理图 配套核心板原理图使用。

This manual is part of the safety documentation related to the Xilinx® Zynq® UltraScale+™ MPSoC and its purpose is to describe the use of the Zynq UltraScale+ MPSoC device in the context of a safety-related system, specifying user responsibilities for installation and operation of these devices in your safety systems to maintain the desired safety integrity level. This safety manual is written in compliance with the Automotive Safety Standard ISO-26262, edition 2011/2012, also taking in account the guidance given by the Draft version of ISO-26262 Part 11 available in April 2016 (Part 11, together with the complete Revision 2 of ISO-26262 will be officially published in 2018).

Xilinx官方文档，讲的是UltraScale系列FPGA的存储器IPcore。主要有DDR3/DDR4,LPDDR3,QDR等存储器接口控制协议IPcore，相似于老版本vivado或ISE的MIG(Memory Interface Generator)，此文档的IPcore讲的IPcore本质上也是MIG

UltraZed原理图，基于Zynq UltraScale+ MPSoC，ZU3EG芯片设计，非常具有参考意义！！

Xilinx官网搜集的Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit——官方PDF资料大全

Xilinx ultrascale plus系列芯片原理图参考，具有很高的参考价值，高端芯片使用注意事项在本图中都可以体现。

例程源码，项目移植，硬件设计参考，图像处理，PCIE，AD采集等等

ZYNQ UltraScale 硬件平台 vivado 2018.1开发平台 实现裸机双核系统双串口独立运行打印helloworld！