mtk drm lcm driver porting guide，for kernel-4.14 user drm core.
2022-03-01 18:43:26
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MIPI 规范 2.0 标准文档 （Version 1.0 – MIPI Board Adopted 14 January 2016）
1.1 Scope
Interface protocols as well as a description of signal timing relationships are within the scope of this
document.
Electrical specifications and physical specifications are out of scope for this document. In addition, legacy
interfaces such as DPI-2 and DBI-2 are also out of scope for this document. Furthermore, device usage of
auxiliary buses such as I2C or SPI, while not precluded by this Specification, are also not within its scope.
1.2 Purpose
The Display Serial Interface Specification defines a high-speed serial interface between a peripheral, such as
an active-matrix display module, and a host processor in a mobile device. By standardizing this interface,
components may be developed that provide higher performance, lower power, less EMI and fewer pins than
current devices, while maintaining compatibility across products from multiple vendors.
2022-01-25 11:23:57
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ICN6201 /02 is a bridge chip which receives MIPI DSI inputs and sends LVDS outputs.
MIPI DSI supports up to 4 lanes and each lane operates at 1Gbps maximum; the totally maximum input
bandwidth is 4Gbps ; and the MIPI defined ULPS(ultra - low -power state) is also supported . ICN6201 decodes
MIPI DSI 18bepp RGB666 and 24bpp RGB888 packets.
The LVDS output 18 or 24 bits pixel with 25MHz to 154MHz, by VESA or JEIDA format.
ICN6201 /02 support video resolution up to FHD (1920x1080) and WUXGA (1920x1200).
ICN6201 adopts QFN48 package and ICN6202 adopts QFN40 package.
2022-01-10 19:03:57
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The Display Serial Interface Specification defines protocols between a host processor and peripheral devices that adhere to MIPI Alliance specifications for mobile device interfaces. The DSI specification builds on existing specifications by adopting pixel formats and command set defined in MIPI Alliance
specifications for DBI-2[2], DPI-2[3], and DCS[1].
2021-12-15 18:58:58
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