EDA工程 hello FPGA library ieee;
use ieee.std_logic_1164.all;
entity ex7_part2_top is
port (sw :in std_logic_vector(17 downto 0);
hex0: out std_logic_vector(6 downto 0);
hex1: out std_logic_vector(6 downto 0);
hex2: out std_logic_vector(6 downto 0);
hex3: out std_logic_vector(6 downto 0);
hex4: out std_logic_vector(6 downto 0);
hex5: out std_logic_vector(6 downto 0);
hex6: out std_logic_vector(6 downto 0);
hex7: out std_logic_vector(6 downto 0);
ledr:out std_logic_vector(17 downto 0);
clock_50:in std_logic);
end;
2021-06-30 17:39:15
917B
EDA
1