MIPS_ISA (答案)

在行为VHDL中描述支持以下MIPS ISA子集（即11条指令）的MIPS控制单元（CU） a) 7 Arithmetic/Logical instructions: add, sub, and, or, nor, slt, addi b) 2 Memory reference: lw, sw c) 2 Control transfer: beq, j 所需的MIPS CU的功能，接口和结构如图1所示。CU具有以下接口： • Generics - Instruction width (n_bits_instr = instr_mem_width with default value of 32) - Location of the operation (OP) code least significant bit in the instruction (opcode_start with default value of 26) - Location of the operation (OP) code most significant bit in the instruction (opcode_end with default value of 31) - Location of the function (funct) code least significant bit in the instruction (funct_start with default value of 0) - Location of the function (funct) code most significant bit in the instruction (funct_end with default value of 5) - Total number of supported ALU operations/functions (n_functions_alu with default value of 16) • Inputs - Instruction fetched (Instr -> n_bits_instr bits) • Outputs - Register destination (RegDst -> 1 bit) - Register write enable (RegWrite -> 1 bit) - ALU source (ALUSrc -> 1 bit) - ALU control (ALUControl -> [log2 (n_functions_alu)] bits) - Memory write enable (MemWrite -> 1 bit) - Memory read enable (MemRead -> 1 bit) - Memory to register (MemToReg -> 1 bit) - Conditional branch on equal (BEQ -> 1 bit) - Unconditional branch (J -> 1 bit) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshot, see Figure 2.

在结构和行为VHDL中描述MIPS处理器的单周期（非流水线）版本，该版本支持以下MIPS ISA子集（即11条指令）： a) 7 Arithmetic/Logical instructions: add, sub, and, or, nor, slt, addi b) 2 Memory reference: lw, sw c) 2 Control transfer: beq, j 微体系结构的数据路径和控制路径如图1所示。您的内存地址转换/映射应遵循图2所示的约定。处理器具有以下接口： • Inputs - Clock (clk -> 1 bit) - Asynchronous reset for processor initialization and for mimicking program load (rst -> 1 bit) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshots, see Figure 3.

---Data Memory (Single-Ported Read/Write memory)--- • Generics - Data memory size/depth (data_mem_depth with default value of 117 locations) - Data memory width (data_mem_width with default value of 32 bits) • Inputs - Clock (clk -> 1 bit) - Asynchronous reset (rst -> 1 bit) - Memory write enable (MemWrite -> 1 bit) 1 -> enable writing to data memory, 0 -> disable writing to data memory - Address for read/write operand (A -> n_bits_address bits = 32 bits) - Write Data for write operand (WD -> data_mem_width bits) • Outputs - Read Data for read operand (RD -> data_mem_width bits) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshot, see Figure 2

---Instruction Memory (Single-Ported Read-Only Memory)--- • Generics - Instruction memory size/depth (instr_mem_depth with default value of 39 locations) - Instruction memory width (instr_mem_width with default value of 32 bits) • Inputs - Asynchronous reset for mimicking program load (rst -> 1 bit) - Address for instruction read (A -> n_bits_address bits = 32 bits) • Outputs - Instruction fetched (Instr -> instr_mem_width bits) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshot, see Figure 2.

在行为VHDL中（使用2个并发进程）描述MIPS ALU，该MIPS ALU支持带符号算术和最多16个操作/功能，如图1所示。ALU具有以下接口： • Generics - ALU data bits (n_bits_alu with default value of 32 bits) - Total number of supported operations/functions (n_functions_alu with default value of 16 functions) • Inputs - First input operand (A -> n_bits_alu bits = 32 bits) - Second input operand (B -> n_bits_alu bits = 32 bits) - ALU control (ALUControl -> [log2 (n_functions_alu)] bits) • Outputs - Result output operand (C -> n_bits_alu bits = 32 bits) - Zero flag (zero -> 1 bit) - Overflow flag (overflow -> 1 bit) • In Vivado - Create a blank project - Add design and simulation source files - Run behavioral simulation - Your waveform configuration should be identical to the provided waveform snapshot, see Figure 2.

Tetris-MIPS：这是使用MARS，MIPS Simulator，汇编语言创建的俄罗斯方块游戏

MIPS为美国芯片设计公司，它采用的是精简指令系统计算结构（RISC结构）（与之对应的：（复杂指令集）CISC结构）。MIPS架构的产品多见于工作站（索尼PS2的Emotion Engine处理器）。RISC比CISC的设计更加简单，由于其授权费用低，被INTEL外的大多数厂商使用。同时在设计理念上MIPS强调软硬件协同提高计算机性能，并简化硬件设计。

包含MIPS实验3（使用 MIPS 指令实现求两个数组的点积 ），实验4（使用 MIPS 指令实现冒泡排序法），实验5（指令调度与延迟分支）的报告，实验指导书，以及MIPS模拟器。

1)用硬件描述语言（Verilog）设计MIPS流水线CPU，支持如下指令集： {add,addi,addiu,addu,and,andi,beq,bne,divu,j,jal,jr,lb,lbu ,lhu,lui, lw,multu,mfhi,mflo,or,ori,slt,slti,sltu,sll,sra,srl,sb,sh,sw,sub,sub} 2)用仿真软件Modelsim对有数据冒险和控制冒险的汇编程序进行仿真。