 RTL8370N-VB: Single-chip 8-port gigabit non-blocking switch architecture  Embedded 8-port 10/100/1000Base-T PHY  Each port supports full duplex 10/100/1000M connectivity (half duplex only supported in 10/100M mode)  Full-duplex and half-duplex operation with IEEE 802.3x flow control and backpressure  Supports 9216-byte jumbo packet length forwarding at wire speed  Supports Realtek Cable Test (RTCT) function  Supports 96-entry ACL Rules  Search keys support physical port, Layer2, Layer3, and Layer4 information  Actions support mirror, redirect, dropping, priority adjustment, traffic policing, CVLAN decision, and SVLAN assignment  Supports 5 types of user defined ACL rule format for 64 ACL rules  Optional per-port enable/disable of ACL function  Optional setting of per-port action to take when ACL mismatch  Supports IEEE 802.1Q VLAN  Supports 4K VLANs and 32 Extra Enhanced VLANs  Supports Un-tag definition in each VLAN  Supports VLAN policing and VLAN forwarding decision  Supports Port-based, Tag-based, and Protocol-based VLAN  Up to 4 Protocol-based VLAN entries  Supports per-port and per-VLAN egress VLAN tagging and un-tagging  Supports IVL, SVL, and IVL/SVL  Supports 4096-entry MAC address table with 4-way hash algorithm  Up to 4096 L2/L3 Filtering Database  Supports Spanning Tree port behavior configuration  IEEE 802.1w Rapid Spanning Tree  IEEE 802.1s Multiple Spanning Tree with up to 16 Spanning Tree instances  Supports IEEE 802.1x Access Control Protocol  Port-Based Access Control  MAC-Based Access Control  Guest VLAN  Supports Quality of Service (QoS)  Supports per port Input Bandwidth Control  Traffic classification based on IEEE 802.1p/Q priority definition, physical Port, IP DSCP field, ACL definition, VLAN based priority, MAC based priority, and SVLAN b

USB3.0 千兆网卡，RTL8153的datasheet

千兆以太网RJ45插座手册,需要的快下，不错的资源

RGMII Image通信协议，包括数据格式、IP头部checksum 算法、接收IP数据报检验IP校验和、千兆UDP命令包及寄存器值表示意义

基于FPGA的UDP硬件协议栈， 全部用SystemVerilog写的，不需CPU参与，包括独立的MAC模块。 支持外部phy的配置，支持GMII和RGMII模式。 以下是接口 input clk50, input rst_n, interface to user module input [7:0] wr_data, input wr_clk, input wr_en, output wr_full, output [7:0] rd_data, input rd_clk, input rd_en, output rd_empty, input [31:0] local_ipaddr, //FPGA ip address input [31:0] remote_ipaddr, //PC ip address input [15:0] local_port, //FPGA port number //interface to ethernet phy output mdc, inout mdio, output phy_rst_n, output is_link_up, `ifdef RGMII_IF input [3:0] rx_data, output logic [3:0] tx_data, `else input [7:0] rx_data, output logic [7:0] tx_data, `endif input rx_clk, input rx_data_valid, input gtx_clk, output logic tx_en

BCM5396 and BCM5389/BCM5387 Design Guidelines， 文档编号：538X_5396-AN105-R。538X_5396-AN102-R 04/24/06 Updated。文档页数68页。千兆以太网交换芯片的设计手册，硬件设计必备。

利用千兆网开发视频的朋友，这个资料对你很有用，它是个开发文档。

千兆以太网技术与应用 第一部分 千兆以太网基础 第1章 千兆网之前的以太网 1 1.1 以太网发展简史 1 1.1.1 1973-1982：以太网的产生与DIX联 盟 1 1.1.2 1982-1990：10Mb/s以太网发展成 熟 2 1.1.3 1983-1997：LAN桥接与交换 2 1.1.4 1992-1997：快速以太网 2 1.1.5 1996—今：千兆以太网 3 1.2 以太网流行的原因 3 1.2.1 以太网与令牌环 3 1.2.2 价格取胜 4 1.2.3 DIX贡献出他们唯一的LAN，以太 网...... 5 1.3 以太网像钟摆一样摆动 6 1.4 以太网的命名方法 7 1.5 走向千兆以太网 8

千兆以太网芯片QCA8334-AL3C资料，291页全英文详细datasheet。

RTL8153参考原理图，USB3.0转千兆，保证好用。