dnn-RTL USC DNN系统的RTL和FPGA实现-Sourya，Yinan，Chiye，Mahdi testbench-主文件是tb_mnist.v。 其他文件用于婴儿网络或子模块。 src-所有源代码Verilog文件。 等级制度： DNN.v - whole network layer_block.v - Contains processors, memory, state machines and other small logic for each layer memory_ctr.v - State machine for each layer. Generates control signals for memory (address, enable), counter and mux processor_set.v - FF, BP and UP proces

关于在RTL设计中，如何处理跨时钟域的问题的一篇文档，写的非常详细。

There are several books about hardware verification, so what makes this book different? Put simply, this book is meant to be useful in your day-to-day work—which is why we refer to it throughout as a handbook. The authors are like you, cube dwellers, with battle scars from developing chips. We must cope with impossible schedules, a shortage of people to do the work, and constantly mutating hardware specifications. We subtitled this book An Object-Oriented Framework because a major theme of the book is how to use object-oriented programming (OOP) to do verification well. We focus on real-world examples, bloopers, and code snippets. Sure, we talk about programming theory, but the theme of this book is how to write simpler, adaptable, reusable code. We focus mainly on OOP techniques because we feel that this is the best way to manage the ever-increasing complexity of verification. We back this up with open-source Verification Intellectual Property (VIP), several complete test systems, and scripts to run them.

SystemVerilog for Verification(3rd)

1小时玩转数字电路.rar AHB-SRAMC和FIFO的设计与验证.rar clock skew.rar IC攻城狮求职宝典.rar linux basic.rar Linux EDA虚拟机 - 个人学习IC设计.rar Perl语言在芯片设计中的应用.rar SoC芯片设计技能专题.rar SystemVerilog Assertion断言理论与实践.rar SystemVerilog_Assertions_应用指南-源代码.rar uvm-1.2.rar VCS_labs.rar Verdi 基础教程.rar Verilog RTL 编码实践.rar [Cadence.IC设计.全资料教

IEEE Std 1800-2005(System Verilog)

IEEE-1800-2012-SystemVerilog

SystemVerilog的听课学习笔记，包括讲义截取、知识点记录、注意事项等细节的标注。

systemverilog编程资料，用于验证

关于systemverilog的学习笔记，适合初学者参考，sv入门