ABSTRACT
In the last few years, power dissipation has become an important design constraint, on par with
performance, in the design of new computer systems. Whereas in the past, the primary job
of the computer architect was to translate improvements in operating frequency and transistor
count into performance, now power efficiency must be taken into account at every step of the
design process.
While for some time, architects have been successful in delivering 40% to 50% annual
improvement in processor performance, costs that were previously brushed aside eventually
caught up. The most critical of these costs is the inexorable increase in power dissipation and
power density in processors. Power dissipation issues have catalyzed new topic areas in computer
architecture, resulting in a substantial body of work on more power-efficient architectures.
Power dissipation coupled with diminishing performance gains, was also the main cause for
the switch from single-core to multi-core architectures and a slowdown in frequency increase.
This book aims to document some of the most important architectural techniques that
were invented, proposed, and applied to reduce both dynamic power and static power dissipation
in processors and memory hierarchies. A significant number of techniques have been proposed
for a wide range of situations and this book synthesizes those techniques by focusing on their
common characteristics.
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