这是从外网好不容易找到的，上传与大家共享，不要积分随便下！我也是下载的，不是自己发明的，如果再去要下载积分，人品还不至于这么差！ 里面有加密的，官方说明是这样的：There are two encrypted verilog files in the "DE2_70_TV_PIP" demonstraction. If users want to modify this demonstration and re-compile the project, please perform the following steps: 1.Use Notepad or other text edit software to open the file "Teraisc_license.dat", which is located in the "DE2_70_demonstrations/License for encrypted IP" folder of the DE2-70 System CD-ROM. 2. The license contains the FEATURE lines required to license the IP Cores as shown below FEATURE 535C_0009 alterad 9999.12 permanent uncounted D702CF471AC0 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="0F45 927A 00F9 DBF3 3AAB D703 4F3D 2406 B374 \ 0E5C 87A1 34BA 10C6 0C08 E554 183B BD2D B79D D64E 3F98 393E \ 94FB F798 07B8 C334 C8B6 D1E4 36F5 67D5 1690" FEATURE 535C_000A alterad 9999.12 permanent uncounted F7FD875F1A28 \ VENDOR_STRING="ddddddddhbilhyyyyyyyyUCIwiFFFFFFFF170M8XXXXXXXXpLsGcTTTTTTTTt7X8GAAAAAAAAbEQP0hhhhhhhhgrtJieeeeeeeebTNOVJJJJJJJJBLNGkuuuuuuuuDLxzRPPPPPPPPW01t4" \ HOSTID=ANY SIGN="1834 5F1A 9CE6 15FD 9246 A640 66FE 918D 1091 \ A2D0 7DF8 7584 0E78 3732 1F48 0B24 3A92 870A EDAA F6F0 2145 \ 3098 5631 C5E1 4DC2 B14D C81A D30D 5518 63D0" 3.Open your Quartus II license.dat file in a text editor. 4.Copy the all the contents of the Terasic_license.dat and paste it at the end of your Quartus II license file. (Note: Do not delete any FEATURE lines from the Quartus II license file. Doing so will result in a non-usable license file.) 5.Open the "DE2_70_TV_PIP" project from Quartus II and compile this project. 6.After compilation is completed, it will generate a sof file named "DE2_70_TV_PIP_time_limited.sof" 7.Load this sof file into the FPGA and the demonstration will have at most one hour to be modified. In another words, the VGA output will be turned off after one hour. If users want to know more information about this demonstration, please contact us at support@terasic.com.

DE2-115 FPGA开发系统使用说明书和实验指导书，系统使用说明书是中文版，实验指导书是英文版，实验指导书的翻译在上传的另一个文件里https://download.csdn.net/download/weixin_42596755/12367479

本人经过大量调试的成功作品，基于DE2硬件平台，能在电脑显示器上显示出彩条信号，全蓝，全绿等色彩，软件开发环境是Quartus II 7.2+Nios II 7.2 IDE.

DE2-115开发板的中文说明书，详细介绍了开发板的使用，而且还有很多高级的设计例子，对初学者很适用！

该代码主要基于Altera DE2 FPGA开发平台,通过读取存储在SD卡中的音频文件，实现音乐播放，读者还可以在此基础上没进一步扩展其功能，希望大家喜欢……

本设计采用DE2开发板，用Verilog实现了基础时钟功能，可以设置起始时间。显示在数码管上。

基于Verilog HDL及DE2开发板的数字钟设计，使用Verilog HDL实现

对de2的详细介绍，而且是中文版的，自己看了觉得很详细很有用

verilog VHDL实现的DE2 uart

DE2 友晶科技的开发板，PC端控制面板，可进行各种模拟操作和显示结果。