FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 ); //----------------------------------------------------------- localparam W_IDLE = 1; localparam W_FIFO = 2; localparam R_IDLE = 1; localparam R_FIFO = 2; reg[2:0] write_state; reg[2:0] next_write_state; reg[2:0] read_state; reg[2:0] next_read_state; reg[15:0] w_data; //FIFO写数据 wire wr_en; //FIFO写使能 wire rd_en; //FIFO读使能 wire[15:0] r_data; //FIFO读数据 wire full; //FIFO满信号 wire empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据 always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state; end always@(*) begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcase end assign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end ///产生FIFO读的数据 always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state; end always@(*) begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <=

基于FPGA设计的vga显示测试实验Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; assign vga_out_hs = video_hs; assign vga_out_vs = video_vs; assign vga_out_r = video_r[7:3]; //discard low bit data assign vga_out_g = video_g[7:2]; //discard low bit data assign vga_out_b = video_b[7:3]; //discard low bit data //generate video pixel clock video_pll video_pll_m0( .inclk0(clk), .c0(video_clk)); color_bar color_bar_m0( .clk(video_clk), .rst(~rst_n), .hs(video_hs), .vs(video_vs), .de(video_de), .rgb_r(video_r), .rgb_g(video_g), .rgb_b(video_b) ); endmodule

基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的 TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 timescale 1ps/1ps module top ( input clk, input rst_n, output[1:0] led, output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16 ; //external memory user interface data width parameter ADDR_BITS = 24 ; //external memory user interface address width parameter BUSRT_BITS = 10 ; //external memory user interface burst width parameter BURST_SIZE = 128 ; //burst size wire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clock wire wr_burst_finish; // from external memory controller,burst write finish wire rd_burst_finish; // from external memory controller,burst read finish wire rd_burst_req; // to external memory controller,send out a burst read request wire wr_burst_req; // to external memory controller,send out a burst write request wire[BUSRT_BITS - 1:0] rd_burst_len; // to e

基于FPGA设计的字符VGA LCD显示实验Verilog逻辑源码Quartus工程文件+文档说明,通过字符转换工具将字符转换为 8 进制 mif 文件存放到单端口的 ROM IP 核中，再从 ROM 中把转换后的数据读取出来显示到 VGA 上，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire osd_hs; wire osd_vs; wire osd_de; wire[7:0] osd_r; wire[7:0] osd_g; wire[7:0] osd_b; assign vga_out_hs = osd_hs; assign vga_out_vs = osd_vs; assign vga_out_r = osd_r[7:3]; //discard low bit data assign vga_out_g = osd_g[7:2]; //discard low bit data assign vga_out_b = osd_b[7:3]; //discard low bit data //generate video pixel clock video_pll video_pll_m0( .inclk0 (clk ), .c0 (video_clk ) ); color_bar color_bar_m0( .clk (video_clk ), .rst (~rst_n ), .hs (video_hs ), .vs (video_vs ), .de (video_de ), .rgb_r (video_r ), .rgb_g (video_g ), .rgb_b

FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data ); parameter MEM_DATA_BITS = 16; //external memory user interface data width parameter ADDR_BITS = 24; //external memory user interface address width p

FPGA读取AD芯片AD9238数据并波形显示例程Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire grid_hs; wire grid_vs; wire grid_de; wire[7:0] grid_r; wire[7:0] grid_g; wire[7:0] grid_b; wire wave0_hs; wire wave0_vs; wire wave0_de; wire[7:0] wave0_r; wire[7:0] wave0_g; wire[7:0] wave0_b; wire wave1_hs; wire wave1_vs; wire wave1_de; wire[7:0] wave1_r; wire[7:0] wave1_g; wire[7:0] wave1_b; wire adc_clk; wire adc0_buf_wr; wire[10:0] adc0_buf_addr; wire[7:0] adc0_buf_data; wire adc1_buf_wr; wir

FPGA读取模数转换芯片AD7606数据并波形显示例程Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( input clk, input rst_n, input[15:0] ad7606_data, //ad7606 data input ad7606_busy, //ad7606 busy input ad7606_first_data, //ad7606 first data output[2:0] ad7606_os, //ad7606 output ad7606_cs, //ad7606 AD cs output ad7606_rd, //ad7606 AD data read output ad7606_reset, //ad7606 AD reset output ad7606_convstab, //ad7606 AD convert start //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue ); wire video_clk; wire video_hs; wire video_vs; wire video_de; wire[7:0] video_r; wire[7:0] video_g; wire[7:0] video_b; wire grid_hs; wire grid_vs; wire grid_de; wire[7:0] grid_r; wire[7:0] grid_g; wire[7:0] grid_b; wire wave0_hs; wire wave0_vs; wire wave0_de; wire[7:0] wave0_r; wire[7:0] wave0_g; wire[7:0] wave0_b; wire wave1_hs; wire wave1_vs; wire

FPGA 读写rtc_ds1302实时时钟的Verilog逻辑源码Quartus工程文件+文档说明，RTC芯片型号ds1302，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 module top( //sys input clk, input rst_n, output rtc_sclk, output rtc_ce, inout rtc_data, output [5:0] seg_sel, output [7:0] seg_data ); wire[7:0] read_second; wire[7:0] read_minute; wire[7:0] read_hour; wire[7:0] read_date; wire[7:0] read_month; wire[7:0] read_week; wire[7:0] read_year; seg_bcd seg_bcd_m0( .clk (clk), .rst_n (rst_n), .seg_sel (seg_sel), .seg_data (seg_data), .seg_bcd ({read_hour,read_minute,read_second}) ); ds1302_test ds1302_test_m0( .rst (~rst_n), .clk (clk), .ds1302_ce (rtc_ce), .ds1302_sclk (rtc_sclk), .ds1302_io (rtc_data), .read_second (read_second), .read_minute (read_minute), .read_hour (read_hour), .read_date (read_date), .read_month (read_month), .read_week (read_week), .read_year (read_year) ); endmodule

基于FPGA的数码管扫描实验Verilog逻辑源码Quartus工程文件+文档说明，6个共阳数码管，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。 介绍共阳极数码管扫描的原理，使用 6 位模 10 计数器组成 6 位十进制计数器，将计数器的 值送到数码管扫描模块显示。 module seg_test( input clk, input rst_n, output[5:0]seg_sel, output[7:0]seg_data ); reg[31:0] timer_cnt; reg en_1hz; //1 second , 1 counter enable always@(posedge clk or negedge rst_n) begin if(rst_n == 1'b0) begin en_1hz <= 1'b0; timer_cnt = 32'd49_999_999) begin en_1hz <= 1'b1; timer_cnt <= 32'd0; end else begin en_1hz <= 1'b0; timer_cnt <= timer_cnt + 32'd1; end end wire[3:0] count0; wire t0; count_m10 count10_m0( .clk (clk), .rst_n (rst_n), .en (en_1hz), .clr (1'b0), .data (count0), .t (t0) ); wire[3:0] count1; wire t1; count_m10 count10_m1( .clk (clk), .rst_n (rst_n), .en (t0), .clr (1'b0), .data (count1), .t (t1) ); wire[3:0] count2; wire t2; count_m10 count10_m2( .clk (clk), .rst_n (rst_n), .en (t1), .clr (1'b0), .data (count2), .t (t2) ); wire[3:0] count3; wire t3; count_m10 count10_m3( .clk (clk), .rst_n (rst_n), .en (t2), .clr (1'b0), .data (count3), .t (t3) ); wire[3:0] count4; wire t4; count_m10 count10_m4( .clk (clk), .rst_n (rst_n), .en (t3), .clr (1'b0), .data (count4), .t (t4) ); wire[3:0] count5; wire t5; count_m10 count10_m5( .clk (clk), .rst_n (rst_n), .en (t4), .clr (1'b0), .data (count5), .t (t5) ); wire[6:0] seg_data_0; seg_decoder seg_decoder_m0( .bin_data (count5), .seg_data (seg_data_0) ); wire[6:0] seg_data_1; seg_decoder seg_decoder_m1( .bin_data (count4), .seg_data (seg_data_1) ); wire[6:0] se