网上“一步一步学ZedBoard & Zynq(二)：使用PL做流水灯”的Vivado版，约束文件采用xdc格式
2022-03-25 17:14:11
2.64MB
1
AES_CCM解密部分的硬件实现，全网独一份！！！
首先声明：
1.AES的CCM模式不适合硬件实现，尤其是数据的填充和准备过程（硬件消耗巨大），应当由CPU执行生成，本文代码也是默认已经得到待处理的数据
2.本代码单纯实现了CCM解密验证部分，由于时间和需求的原因没有实现加密部分，由于其加解密的相似性其正向加密也比较简单。
3.本代码中声明了2个AES模块同时运行，并行执行解密和验签的过程，速度较快。
2022-02-16 22:25:21
398KB
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verilog编写的呼吸灯，周期4s，从最暗到最亮2s，从最亮到最暗2s,另附testbench，基于quartus平台实现
2021-12-22 17:05:28
890B
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FPGA源码包括串口网口LED灯SPI等等VHDL Verilog都有，很多例程和自己编写的代码
2021-12-16 19:29:03
54.75MB
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Cyclone10 FPGA读写MP25P16 spiflash实验Verilog源码Quartus17.1工程文件+文档资料,, FPGA为CYCLONE10LP系列中的10CL025YU256C8. 完整的Quartus工程文件，可以做为你的学习设计参考。
module spi_flash_top(
input sys_clk,
input rst,
output nCS,
output DCLK,
output MOSI,
input MISO,
input[15:0] clk_div,
input[3:0] cmd,
input cmd_valid,
output cmd_ack,
input[23:0] addr,
input[7:0] data_in,
input[8:0] size,
output data_req,
output reg[7:0] data_out,
output reg data_valid
);
localparam S_IDLE = 0;
localparam S_SE = 1;
localparam S_BE = 2;
localparam S_READ = 3;
localparam S_WRITE = 4;
localparam S_ACK = 5;
localparam S_CK_STATE = 6; //present state monitor
localparam S_WREN = 7;
wire spi_flash_cmd_ack;
reg[3:0] sub_cmd;
reg sub_cmd_valid;
reg[8:0] sub_size;
reg[4:0] state,next_state;
reg[7:0] state_reg;
wire sub_data_valid;
wire[7:0] sub_data_in;
wire[7:0] sub_data_out;
assign sub_data_in = data_in;
assign cmd_ack = (state == S_ACK);
always@(posedge sys_clk or posedge rst)
begin
if(rst==1)
state <= S_IDLE;
else
state <= next_state;
end
always@(*)
begin
case(state)
S_IDLE:
if(cmd_valid && cmd == `CMD_BE)
next_state <= S_WREN;
else if(cmd_valid && cmd == `CMD_SE)
next_state <= S_WREN;
else if(cmd_valid && cmd == `CMD_READ)
next_state <= S_READ;
else if(cmd_valid && cmd == `CMD_PP)
next_state <= S_WREN;
else
next_state <= S_IDLE;
S_WREN:
if(spi_flash_cmd_ack && cmd == `CMD_BE)
next_state <= S_BE;
else if(spi_flash_cmd_ack && cmd == `CMD_SE)
next_state <= S_SE;
else if(spi_flash_cmd_ack && cmd == `CMD_PP)
next_state <= S_WRITE;
else
next_state <= S_WREN;
S_BE:
if(spi_flash_cmd_ack)
next_state <= S_CK_STATE;//读取状态寄存器
else
next_state <= S_BE;
S_SE:
if(spi_flash_cmd_ack)
next_state <= S_CK_STATE;
2021-12-12 09:08:55
4.81MB