Cyclone4 FPGA读写高速AD-TLC549+DA-AD9708模块实验Verilog逻辑源码Quartus工程+文档资料
module DA_AD9708_BASE (
//input
input sys_clk , //system clock;
// input sys_rst_n , //system reset, low is active;
input [3:0] key ,
//output
output reg [7:0] DA_DATA ,
output reg DA_CLK ,
output reg [7:0] LED
);
//Reg define
reg [7:0] div_cnt ;
//Wire define
//************************************************************************************
//** Main Program
//**
//************************************************************************************
assign sys_rst_n = 1'b1 ;
// counter used for div osc clk to ad ctrl clk 50M/4 = 12.5Mhz
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
div_cnt <= 8'b0;
else
div_cnt <= div_cnt + 8'b1;
end
//gen DA_CLK
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
DA_CLK <= 1'b0 ;
else if ( div_cnt == 8'd0 )
DA_CLK <= ~DA_CLK ;
else ;
end
//display AD sample data to LED
always @(posedge DA_CLK or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
DA_DATA <= 8'b0;
else
DA_DATA <= { key, key };
end
//display AD sample data to LED
always @(posedge DA_CLK or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
LED <= 8'b0;
else
LED <= { key, key } ;
end
2021-09-02 14:08:53
7.17MB
Cyclone2 FPGA读写 ADC_TLC549实验Verilog逻辑源码Quartus工程文件,
module AD_TLC549 (
//input
input sys_clk , //system clock;
input sys_rst_n , //system reset, low is active;
input AD_IO_DATA ,
//output
output reg AD_IO_CLK ,
output reg AD_CS ,
output reg [7:0] LED
);
//Reg define
reg [6:0] div_cnt ;
reg ad_clk ;
reg [4:0] ctrl_cnt ;
reg [7:0] ad_data_shift ;
//Wire define
//************************************************************************************
//** Main Program
//**
//************************************************************************************
// counter used for div osc clk to ad ctrl clk 50M/64 = 0.78Mhz
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
div_cnt <= 6'b0;
else
div_cnt <= div_cnt + 6'b1;
end
//gen ad_clk
always @(posedge sys_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
ad_clk <= 1'b0 ;
else if ( div_cnt <= 6'd31 )
ad_clk <= 1'b1 ;
else
ad_clk <= 1'b0 ;
end
// ad ctrl signal gen
// ctrl_cnt 0 - 32is for ad ctrl
always @(posedge ad_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
ctrl_cnt <= 5'b0;
else
ctrl_cnt <= ctrl_cnt + 5'b1;
end
always @(posedge ad_clk or negedge sys_rst_n) begin
if (sys_rst_n ==1'b0)
AD_IO_CLK <= 1'b0;
else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10
|| ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16
|| ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 ) // ad clk low
AD_IO_CLK <= 1'b1;
else
AD_IO_CLK <= 1'b0;
end
always @(posedge ad_clk or negedge sys_rst
2021-09-02 14:04:15
1.53MB
cyclone4 FPGA读写8位AD转换器TLC549实验Verilog逻辑源码Quartus11.0工程文件, FPGA型号为EP4CE6E22C8,可以做为你的学习设计参考。
(
clk, //系统50MHZ时钟
adc_sclk, //AD TLC549的时钟
data, //AD TLC549的数据口
cs, //AD TLC549的片选择
wei, //数码管的为选择
duan //数码管的7段码
);
input clk;
input data;
output cs;
output adc_sclk;
output[7:0] duan;
output[3:0] wei;
reg cs,adc_sclk,clk1k,clk1ms;
reg[15:0] count;
reg[24:0] count1ms;
reg[3:0] cnt;
reg[2:0] number;
reg[1:0] state;
reg[3:0] wei;
reg ledcs;
reg [7:0] duan;
reg[7:0] dataout;
reg[16:0] tenvalue;
parameter sample=2'b00,
display=2'b01;
/**********产生100k的采集时钟信号*********/
always@(posedge clk)
begin
if(count<=250)
count<=count+1'b1;
else
begin
count<=0;
adc_sclk25'd25000)
begin
clk1ms<=~clk1ms;
count1ms<=0;
end
else
count1ms<=count1ms+1;
end
/*********AD采样程序**************/
always@(negedge adc_sclk)
begin
case(state)
sample:
begin
cs<=0;
dataout[7:0]4'd7)
begin
cnt<=0;
state<=display;
end
else
begin
cnt<=cnt+1;
state<=sample;
end
end
display:
begin
cs<=1;//关AD片选
tenvalue>4)&8'b0000_1111)*16+ tendata(dataout&8'b0000_1111))*129;//
//得到采集的数据
state<=sample;
end
default: state<=display;
endcase
end
/***********2进制转十进制函数*************/
function[7:0] tendata;//返回一个4位的数字
input[7:0] datain;
begin
case(datain)
4'b00000000: tendata=4'd0;//0
4'b00000001: te
2021-08-20 19:08:33
5.73MB
本实验的内容是 利用状态机实现对 TLC549TLC549TLC549TLC549TLC549TLC549的采样控制，作一个 简易 的电 压表。实验 压表。实验 时通过 调节电位器 RW1 RW1改变 ADC ADC的模拟输入值，数据采样读取后由 模拟输入值，数据采样读取后由 数码管显示，最后用万表测量输入电压并与读取到的据（ 数码管显示，最后用万表测量输入电压并与读取到的据（ 数码管显示，最后用万表测量输入电压并与读取到的据（ 数码管显示，最后用万表测量输入电压并与读取到的据（ 数码管显示，最后用万表测量输入电压并与读取到的据（ 经换算后的数据 ， 单位为 MV ）作比较 。
2021-07-01 16:36:21
769KB
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