Infineon-AURIX_TC3xx_Part2-UserManual-v1.5.0-2/2
2021-09-09 16:43:41
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Infineon-AURIX_TC3xx_Part2-UserManual-v1.5.0 1/2
2021-09-09 16:35:00
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AURIX 2G Generation startup and
initialisation
2021-07-05 13:02:24
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AP32363_MCMCAN_GettingStarted_v2.2
2021-07-05 13:02:20
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This Target Specification describes the Infineon AURIX™ TC3xx Platform family, a range of 32-bit multicore
microcontrollers based on the Infineon TriCore™ Architecture.
This family document covers the superset functionality. It is supplemented by a separate device specific
document “Appendix” that covers differences of a particular device to this family superset.
2021-05-08 10:53:38
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The AURIX™ TC3xx Platform has three independent on-chip connectivity resources:
• System Resource Interconnect Fabric (SRI Fabric)
• System Peripheral Bus (SPB)
• Back Bone Bus (BBB)
The SRI Fabric connects the TriCore CPUs, the DMA module, and other high bandwidth requestors to high
bandwidth memories and other resources for instruction fetches and data accesses.
2019-12-21 19:50:25
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