Cyclone2 FPGA读写SRAM IS61LV25616 实验Verilog逻辑源码Quartus工程文件 module SRAM_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] SRAM_DQ , output reg [17:0] SRAM_ADDR , output reg SRAM_CE , output reg SRAM_OE , output reg SRAM_WE , output reg SRAM_UB , output reg SRAM_LB , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg sram_clk ; reg [5:0] ctrl_cnt ; reg [15:0] sram_data_lck ; reg [15:0] sram_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to sram ctrl clk 50M/16 always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen sram_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) sram_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) sram_clk <= 1'b1 ; else sram_clk <= 1'b0 ; end // sram ctrl signal gen // ctrl_cnt 0 - 31 is for write ctrl // ctrl_cnt 31 - 63 is for read ctrl always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 6'b0; else ctrl_cnt <= ctrl_cnt + 6'b1; end always @(posedge sram_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) SRAM_ADDR <= 18'b0; else if ( ctrl_cnt

Cyclone2 FPGA读写FLASH SST39VF1601 实验Verilog逻辑源码Quartus工程文件 module FLASH_TEST ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output inout [15:0] FLASH_DQ , output reg [20:0] FLASH_ADDR , output reg FLASH_CE , output reg FLASH_OE , output reg FLASH_WE , output reg FLASH_RST , output reg [ 7:0] LED ); //Reg define reg [3:0] div_cnt ; reg flash_clk ; reg [31:0] wait_cnt ; reg [5:0] ctrl_cnt ; reg [15:0] flash_data_lck ; reg [15:0] flash_din ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to flash ctrl clk 50M/16 , one flash ctrl clk cycle is 330ns always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 4'b0; else div_cnt <= div_cnt + 4'b1; end //gen flash_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) flash_clk <= 1'b0 ; else if ( div_cnt <= 4'd7 ) flash_clk <= 1'b1 ; else flash_clk <= 1'b0 ; end // flash ctrl signal gen // read FLASH devid need 5 step : // ctrl_cnt 10 - 13 is write oxaa in addr 0x5555 // ctrl_cnt 14 - 17 is write ox55 in addr 0x2aaa // ctrl_cnt 18 - 21 is write ox90 in addr 0x5555 // ctrl_cnt 22 -30 is wait time for TIDA // ctrl_cnt 31 -34 is read manId in addr 0 // ctrl_cnt 35 -38 is read devid in addr

Cyclone2 FPGA读写DAC_TLC5620实验Verilog逻辑源码Quartus工程文件 module DA_TLC5620 ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; //output output reg DA_IO_CLK , output reg DA_LOAD , output reg DA_LDAC , output reg DA_OUT_DATA , output reg [7:0] LED ); //Reg define reg [6:0] div_cnt ; reg da_clk ; reg [4:0] ctrl_cnt ; reg [15:0] delay_cnt ; reg [ 7:0] analog_data ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to da ctrl clk 50M/64 = 0.78Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 6'b0; else div_cnt <= div_cnt + 6'b1; end //gen da_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) da_clk <= 1'b0 ; else if ( div_cnt <= 6'd31 ) da_clk <= 1'b1 ; else da_clk <= 1'b0 ; end // da ctrl signal gen // ctrl_cnt 0 - 32 is for da ctrl always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 5'b0; else ctrl_cnt <= ctrl_cnt + 5'b1; end always @(posedge da_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_IO_CLK <= 1'b0; else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10 || ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16 || ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 || ctrl_cnt == 5'd22 || ctrl_

Cyclone4 FPGA读写高速AD-TLC549+DA-AD9708模块实验Verilog逻辑源码Quartus工程+文档资料 module DA_AD9708_BASE ( //input input sys_clk , //system clock; // input sys_rst_n , //system reset, low is active; input [3:0] key , //output output reg [7:0] DA_DATA , output reg DA_CLK , output reg [7:0] LED ); //Reg define reg [7:0] div_cnt ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ assign sys_rst_n = 1'b1 ; // counter used for div osc clk to ad ctrl clk 50M/4 = 12.5Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 8'b0; else div_cnt <= div_cnt + 8'b1; end //gen DA_CLK always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_CLK <= 1'b0 ; else if ( div_cnt == 8'd0 ) DA_CLK <= ~DA_CLK ; else ; end //display AD sample data to LED always @(posedge DA_CLK or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) DA_DATA <= 8'b0; else DA_DATA <= { key, key }; end //display AD sample data to LED always @(posedge DA_CLK or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) LED <= 8'b0; else LED <= { key, key } ; end

Cyclone2 FPGA读写 ADC_TLC549实验Verilog逻辑源码Quartus工程文件, module AD_TLC549 ( //input input sys_clk , //system clock; input sys_rst_n , //system reset, low is active; input AD_IO_DATA , //output output reg AD_IO_CLK , output reg AD_CS , output reg [7:0] LED ); //Reg define reg [6:0] div_cnt ; reg ad_clk ; reg [4:0] ctrl_cnt ; reg [7:0] ad_data_shift ; //Wire define //************************************************************************************ //** Main Program //** //************************************************************************************ // counter used for div osc clk to ad ctrl clk 50M/64 = 0.78Mhz always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) div_cnt <= 6'b0; else div_cnt <= div_cnt + 6'b1; end //gen ad_clk always @(posedge sys_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ad_clk <= 1'b0 ; else if ( div_cnt <= 6'd31 ) ad_clk <= 1'b1 ; else ad_clk <= 1'b0 ; end // ad ctrl signal gen // ctrl_cnt 0 - 32is for ad ctrl always @(posedge ad_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) ctrl_cnt <= 5'b0; else ctrl_cnt <= ctrl_cnt + 5'b1; end always @(posedge ad_clk or negedge sys_rst_n) begin if (sys_rst_n ==1'b0) AD_IO_CLK <= 1'b0; else if ( ctrl_cnt == 5'd6 || ctrl_cnt == 5'd8 || ctrl_cnt == 5'd10 || ctrl_cnt == 5'd12 || ctrl_cnt == 5'd14 || ctrl_cnt == 5'd16 || ctrl_cnt == 5'd18 || ctrl_cnt == 5'd20 ) // ad clk low AD_IO_CLK <= 1'b1; else AD_IO_CLK <= 1'b0; end always @(posedge ad_clk or negedge sys_rst

FPGA读写SDRAM page fifo实验完整Verilog逻辑源码Quartus工程文件, Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 module sdram_read_write( clk, reset_n, state_signal, rw_done_signal, ar_done_signal, sdram_bank_addr, write_data, read_data, io_ctl, sdram_command, sdram_address, sdram_dqm, sdram_data ); //参数定义 //端口定义 input clk; //时钟信号100MHz input reset_n; //复位信号，低电平有效 input [2:0] state_signal; //状态信号，用于控制对SDRAM进行读写和自刷新 input [21:0] sdram_bank_addr; //SDRAM最小单元地址，[21:20]块地址+[19:8]行地址Row+[7：0]列地址Column input [15:0] write_data; //写入SDRAM的数据 input io_ctl; output rw_done_signal; //读写完成信号 output ar_done_signal; //自动刷新完成信号 output [15:0] read_data; //从SDRAM读出的数据 output [4:0] sdram_command; //SDRAM指令，cke、cs_n、ras、cas_n、we_n，SDRAM指令信号 output [13:0] sdram_address; //SDRAM读写地址 output [1:0] sdram_dqm; //SDRAM数据掩码 inout [15:0] sdram_data; //sdram读写数据 //常量定义 parameter NOP = 5'b10111, //空操作 ACTIVE = 5'b10011, //行激活 READ = 5'b10101, //读操作 WRITE = 5'b10100, //写操作 PR = 5'b10010, //预充电 AR = 5'b10001, //自刷新 LMR = 5'b10000, //设置寄存器 BURST_STOP = 5'b10110; //突发停止指令 parameter ar_state = 3'b001, //自刷新状态 re

FPGA读写SDRAM read_write_a_worde实验完整Verilog逻辑源码Quartus工程文件， Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 `timescale 1 ns/ 1 ps // synopsys translate_on module sdram_top( clk, reset_n, sdram_bank_addr, write_data, read_data, read_req, write_req, rw_ack, bus_signal, init_done, sdram_clk, sdram_data, sdram_command, sdram_address, sdram_dqm ); // 系统信号 input clk; //20M系统时钟 input reset_n; //复位信号，低电平有效 // 内部信号 input [21:0] sdram_bank_addr; //读写SDRAM的地址 input [15:0] write_data; //写如sdram的数据 output [15:0] read_data; //从sdram读出的数据 input read_req; //读数据请求信号 input write_req; //写数据请求信号 output rw_ack; //读写应答信号 output bus_signal; //忙信号 output init_done; //初始化完成信号，输出，高电平有效 // SDRAM接口信号 output sdram_clk; //sdram时钟信号 inout [15:0] sdram_data; //sdram读写数据 output [4:0] sdram_command; //cke、cs_n、ras、cas_n、we_n，SDRAM指令信号 output [13:0] sdram_address; //[13:12]BA , [11:0]Addr，SDRAM地址信号 output [1:0] sdram_dqm; //SDRAM数据掩码 //连接线 wire init_start; //初始化开始信号,高电平有效 wire [4:0] sdram_init_command; //cke、cs_n、ras、cas_n、we_n，SDRAM指令信号 wire [4:0] sdram_rw_command; //cke、cs_n、ras、cas_n、we_n，SDRAM指令信号 wire [13:0] sdram_init_address; //[13:12]BA , [11:0]Addr，SDRAM地址信号 wire [13:0] sdram_rw

FIFO full_adder SPI接口 分頻器等9个VHDL设计源码Quartus工程文件， Quartus软件版本9.0,可以做为你的学习设计参考。 library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity spi_in is port( sck_in:in std_logic; mosi:in std_logic;--收 miso:out std_logic;--发 data_out:out std_logic_vector(7 downto 0) ); end spi_in; architecture spi_behave of spi_in is signal gain_data:std_logic_vector(7 downto 0); signal num:integer range 0 to 9; begin process(sck_in) begin if(sck_in'event and sck_in='1')then if(num=9)then num<=0; else num0 and num<9)then gain_data(9-num)<=mosi; else data_out<=gain_data; end if; end process; end spi_behave;

FPGA读写SDRAM page实验完整Verilog逻辑源码Quartus工程文件, Quartus软件版本11.0, FPGA型号为CYCLONE4E系列中的EP4CE6E22C8,可以做为你的学习设计参考。 // synopsys translate_off `timescale 1 ns/ 1 ps // synopsys translate_on module sdram_top( clk, sdram_100mhz, reset_n, sdram_bank_addr, write_data, read_data, read_req, write_req, rw_ack, bus_signal, init_done, sdram_clk, sdram_data, sdram_command, sdram_address, sdram_dqm ); // 系统信号 input clk; //100M系统时钟 input sdram_100mhz; //100Msdram时钟 input reset_n; //复位信号，低电平有效 // 内部信号 input [21:0] sdram_bank_addr; //读写SDRAM的地址 input [15:0] write_data; //写如sdram的数据 output [15:0] read_data; //从sdram读出的数据 input read_req; //读数据请求信号 input write_req; //写数据请求信号 output rw_ack; //读写应答信号 output bus_signal; //忙信号 output init_done; //初始化完成信号，输出，高电平有效 // SDRAM接口信号 output sdram_clk; //sdram时钟信号 inout [15:0] sdram_data; //sdram读写数据 output [4:0] sdram_command; //cke、cs_n、ras、cas_n、we_n，SDRAM指令信号 output [13:0] sdram_address; //[13:12]BA , [11:0]Addr，SDRAM地址信号 output [1:0] sdram_dqm; //SDRAM数据掩码 //连接线 wire init_start; //初始化开始信号,高电平有效 wire [4:0] sdram_init_command; //cke、cs_n、ras、cas_n、we_n，SDRAM指令信号 wire [4:0] sdram_rw_command; //cke、cs_n、ras、cas_n、we_n，SDRAM指令信号 wire

2N分頻器5分頻器10分頻器分頻器器VHDL逻辑设计源码Quartus工程文件, Quartus软件版本9.0,可以做为你的学习设计参考。 ibrary ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity clk_8div is port( clk:in std_logic; clk_div2:out std_logic; clk_div4:out std_logic; clk_div8:out std_logic); end clk_8div; architecture rtl of clk_8div is signal counter :std_logic_vector(2 downto 0); begin process(clk) begin if(clk'event and clk='1') then if(counter="111") then counter'0'); else counter<=counter+1; end if; end if; end process; clk_div2<=not counter(0);--ȡ��һλ clk_div4<=not counter(1); clk_div8<=not counter(2); end rtl;